Transtech Transputer, User Manual

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The TRAM Standard
TMB M 711 Transputer Motherboard User Manual
19
Figure 18 shows the pinout of a size 1 TRAM.
The TRAM brings out all four of the transputer’s links for connection
to other TRAMs.
LinkSpeedA and LinkSpeedB control the operating
speed of the transputer’s links. Asserting both of these pins high
causes the links to operate at 20Mbits/sec, deasserting both these
pins low causes the links to operate at 10Mbits/sec. Other
combinations of states of these two signals are illegal.
The transputer’s error , analyse and reset signals are brought out
from the TRAM. The reset and analyse signals are taken directly to
the transputer and allow the transputer to be programmed and
debugged. The error output from the transputer is buffered by a
transistor on the TRAM. This has the effect of inverting the signal (it
becomes
notError
) and also makes the signal an open collector
output. This allows wire-ORing of the error signals allowing any
TRAM to signal error back to the host computer.
The other pins of the TRAM provide power to the circuitry and a clock
for the transputer. Note that the input clock signal for the transputer
is multiplied by an on chip Phase Locked Loop to give the final
processor clock (typically 20 to 35 MHz).
3.2.2.2 Subsystem Signals
In order to be able to manage a network of transputers the error,
analyse and reset signals are taken to the host computer. However,
it is often convenient to be able to drive these signals from a
master
transputer. These signals are collectively known as the subsystem
signals. Most TRAMs have a subsystem port which allows them to
Link2Out
Link2In
Vcc
Link1Out
Link1In
LinkSpeed A
LinkSpeed B
ClockIn (5MHz)
Link3In
Link3Out
Gnd
Link0In
Link0Out
notError
Reset
Analyse
Link0 Link1
Link2 Link3
1
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Figure 18. Pinout of Size 1 TRAM (not to scale)