Transtech Transputer, User Manual

Page: 102 / 200

VMEbus Interface
94
Transputer Motherboard User Manual TMB M 711
8.2.1 Link Adaptor Registers
The first four locations are mapped to a C012, as shown in table 33.
• Input Data Register: this register contains the last data byte
received from the VMEbus link. Its contents are not valid unless
the Data Present flag in the Input Status Register is asserted
(set).
• Input Status Register: this register contains the Data Present flag
(bit 0 - least significant bit) and Input Interrupt Enable bit (bit
1).The Data Present flag is set to indicate reception and latching
of a data byte. Setting the Input Interrupt Enable bit will cause the
C012 to generate an interrupt whenever this condition arises. Bits
2-7 are not used and must be written as zero’s.
• Output Data Register: data written to this register is transmitted
out of the VMEbus link. Data may only be written when the
Output Ready flag in the Output Status register is set.
• Output Status Register: this register contains the Output Ready
flag (bit 0 - least significant bit) and the Output Interrupt Enable
bit. The Output Ready flag is set to indicate that the Output Data
Register is ready for the next byte to be transmitted. Setting the
Output Interrupt Enable bit will cause the C012 to generate an
interrupt whenever this condition arises. Bits 2-7 are not used
and must be written as zero’s.
Byte Offset Bits R/W Description
#01 7 to 0 Read Input Data
#03 7 to 0 Write Output Data
#05 0 Read Input Data Present
1 Write Input Interrupt Enable
#07 0 Read Output Ready
1 Write Output Interrupt Enable
Table 33: C012 Registers