Transtech Transputer, User Manual

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The TRAM Standard
TMB M 711 Transputer Motherboard User Manual
33
3.4.3 System Control Interface
The next three registers in the IO space are the system control
registers. In terms of function they are identical to the subsystem
latches on some TRAMs. Only bit 0 of these registers is used:
Reset register: setting bit 0 to ‘1’ asserts Reset to the
motherboard, clearing bit 0 to ‘0’ deasserts
Reset.
Analyse register: Setting bit 0 to ‘1’ asserts analyse to the
motherboard, clearing bit 0 to ‘0’ deasserts
analyse.
Error register: Reading a ‘1’ from bit 0 indicates an Error
on the motherboard, Reading a ‘0’ from bit
0 indicates no Error.
3.4.4 Interrupts and DMA
Two other registers are provided on Transtech’s range of
motherboards are not part of the basic “B004” interface. The two
other registers provide support for allowing DMA access to the link
hardware. This overcomes the inherent inefficiency of software
polling for every single byte read or written to the link adapter,
however these features are not often used. No standard software
from Transtech uses these features.
The PC contains a DMA controller chip (the 8237) which is employed
for these high speed transfers. A DMA transfer to the to the
motherboard is initiated by writing a ‘0’ to the DMA request register.
A DMA transfer from the motherboard is initiated by writing a ‘1’ to
the DMA request register.
To discover when the DMA has completed it is possible to poll the
status of the DMA controller chip. However, a better method is to
generate an interrupt to the PC. For this purpose the last register in
the motherboard IO space is the interrupt control register. This
register is a mask register allowing the PC to be interrupted on any
combination of four events. Figure 29 shows the structure of this
register.