Themis USPIIi-1v, Hardware Manual

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USPIIi-1v Hardware Manual
7-4
Themis Computer
7.3.3 VMEbus Resets
A system reset from the VMEbus is received by the Universe IIB ASIC through the VME P1 connector. The
Universe IIB asserts LOCAL_RESET to the EPLD. The EPLD will de-assert POWER_OK to the RIC when
it receives LOCAL_RESET and initiate the same reset sequence as explained in the above section (refer to
Section 7.3.2, "Power Management Resets," on page 7-3).
An incoming VMEbus may be enabled or disabled through the setting of jumper JP3901. If JP3901 is
installed to 1-2 the USPII
i -1v may be reset from the VMEbus. If JP3901 is installed to 2-3 or left open, resets
from the VMEbus will be disabled.
Outgoing VMEbus resets may also be enabled and disabled by setting jumper JP3801. If JP3801 is installed
to 1-2 a reset of the USPII
i -1v will be propagated through the Universe IIB distributed through the VMEbus.
If JP3801 is installed to 2-3 or left open a reset of the USPII i -1v will not be propagated to the VMEbus.
Software may initiate a VMEbus Reset by writing to VME_Software_Reset address located at
0x1FF.F110.0001. A Software VMEbus Reset will reset only the VMEbus. No components on the USPII
i -1v
are effected by a Software VMEbus Reset.
7.3.4 3-Level Watchdog Resets
A 3-Level Watchdog is implemented in the FPGA as explained in Section 6.1.3, "3-Level Watchdog," on
page 6-2. When the second watchdog in the FPGA expires, the FPGA asserts XIR to the RIC which
propagates the signal to the UltraSPARC-II
i . This signal initiates an XIR in the processor. An XIR is not
propagated through the system. Only the processor is effected.
When the third watchdog in the FPGA expires, the FPGA assets POR to the RIC which propagates the signal
to the UltraSPARC-II
i . This signal initiates a POR in the processor, which is propagated throughout the
system.
Note — The 3-Level Watchdog is different from a Watchdog implemented internally on the UltraSPARC-
II i . Refer to Section 7.2.3, "Watchdog Reset (WDR)," on page 7-2 for more information concerning the
Watchdog Reset implemented internally on the UltraSPARC-II i .
7.3.5 Software POR
Software may initiate a reset equivalent to a Power-On-Reset (POR) by setting the SOFT_POR bit in the
UltraSPARC-II
i Reset_Control Register (Table 7-1 ‘UltraSPARC-IIi Reset_Control Register,’ on page 7-5).
This bit will remain set until software clears it, to allow software to detect the source of the reset.
7.3.6 Software XIR
Software may initiate a reset equivalent to an Externally-Initiated-Reset (XIR) by setting the SOFT_XIR bit
in the UltraSPARC-II
i Reset_Control Register (Table 7-1 ‘UltraSPARC-IIi Reset_Control Register,’ on page
7-5). This bit will remain set until software clears it, to allow software to detect the source of the reset.