Themis USPIIi-1v, Hardware Manual

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Themis Computer
4-1
4
4 Hardware Overview
4.1 Major Components
The following sections provide a description of the major of the USPII i -1v. More detailed explanations of
certain subsystems is provided in later sections and chapters.
4.1.1 SME UltraSPARC-II i Processor and Cache
The Central Processor for the USPII i -1v is the UltraSPARC-II i (SME: SME1430). There are two versions of
CPU available, the UltraSPARC II i -360 and the UltraSPARC II i -440. The architecture complies with SPARC
V9 instruction set, which enables the system to use a wide range of peripherals and the high performance
Solaris 2.6 operating system. For further details on the UltraSPARC-II
i CPU refer to the “USPIIi-1v Software
Manual”, or the SME1430 Highly Integrated 64-bit RISC Processor, PCI Interface Data Sheet , SUN
document number 805-0086-02, and the UltraSPARC-IIi User’s Manual , SUN part number 805-0087-01.
4.1.2 E-Cache
The E-Cache (also referred to as “Level 2 Cache”) is a unified, write-back, allocating-on-misses, direct
mapped cache. The E-Cache is physically indexed and physically tagged (PIPT) and has no virtual or context
information. Except for stable storage and error management, the operating system requires no knowledge of
the E-Cache after initialization. The E-Cache includes the content of the Instruction Cache (I-Cache) and the
Data Cache (D-Cache). For more information on the I-Cache and D-Cache, Section 5.2.6, "Instruction and
Data Cache (I- and D- Cache)," on page 5-3.
The USPII i -1v E-Cache uses a fast Register-Latch access mode. In the Register-Latched mode (also referred
to as “2-2”) the E-Cache Static RAMs have a cycle time equal to twice the processor cycle time. Depending
on the grade of UltraSPARC-II
i processor ordered, the SRAM access time will either be 4.5 nanoseconds, for
the 440 MHz processor, or 5.5 nanoseconds for the 360 MHz processor. In the Register-Latched mode, two
processor clocks are consumed to send the address and two processor clocks are consumed to return the E-
Cache data giving a 4-cycle pin-to-pin latency. As a result of the tight control over the SRAM turn on and
turn off times, no dead cycles are necessary when alternating between reads and writes.
Memory accesses to the E-Cache must be cacheable. Consequently, no E-Cache enable bit is present in the
LSU_Control_Register (Refer to
Table 5-4, "LSU_Control_Register," on page 5-12). Instruction fetches are
directed to non-cacheable PCI or UPA64S space when any of the following conditions are true: