Themis USPIIi-1v, Hardware Manual

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USPIIi-1v Hardware Manual
5-2
Themis Computer
5.2 USPIIi-1v and the Universe IIB PCI Interface
The following table lists some of the PCI signals of the USPIIi-1v to the Universe IIB’s PCI interface.
5.3 VMEbus Interface
5.3.1 VMEbus Configuration
The following lists the initial configuration of the VMEbus system:
• VMEbus First Slot Detector
• Two methods of Auto Slot ID
• Register Access at the power up
5.3.2 Universe IIB as the VMEbus Slave
The Universe IIB’s VMEbus Slave Channel supports all of the addressing and data transfer modes which are
documented in the VME64 specification. The Universe IIB does not support the A64 mode and the modes
intended to augment the 3U applications, i.e. A40 and MD32. The Universe II becomes a slave when one of
its eight programmed slave images or register images are accessed by a VMEbus master. It is not implied that
the Universe II cannot reflect a cycle on the VMEbus and access itself, as it is capable of doing so. Depending
on the programmed values of the VMEbus slave images, the incoming write transaction from the VMEbus
may be treated as either posted or coupled (refer to Section 5.4, "Slave Image Programming," on page 5-7). If
the post write operation is selected, the data is written to a Posted Write Receive FIFO (RXFIFO) and the
VMEbus master receives the data acknowledgment from the Universe IIB. The Universe IIB transfers the
write data from the RXFIFO without the involvement of the initiating VMEbus master (refer to “Posted
Writes” on page 2-15 of the Universe IIB manual for a complete explanation of this operation). If the coupled
Table 5-1. Universe IIB PCI Interface Pins
Universe IIB Pins
USPIIi-1v
Primary PCI Bus
Signals
Description
AD[31..0] AAD<31..0> 32-bit PCI Bus interface
LCLK U2_CLK 33MHz
IDSEL AAD<12> Primary PCI Bus Address 12
REQ# AREQ_L<0> PCI Bus Request 0
GNT# AGNT_L<0> PCI Bus Grant 0
LINT_0# U2_LINT_L<0> PCI IRQ 0
LINT_[7..1]# Pulled up. Unused PCI IRQs