Themis USPIIi-1v, Hardware Manual

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USPIIi-1v Hardware Manual
4-2
Themis Computer
• The I-MMU is disabled
• The UltraSPARC-II
i is in RED_state
• The access is mapped by the I-MMU as physically non-cacheable
Data accesses to non-cacheable PCI or UPA64S space occur when either:
• The D-MMU enable bit (DM) in the LSU_Control_Register is clear, or
• The access is mapped by the D-MMU as non-physical cacheable (unless ASI_PHYS_USE-EC is used).
Note — When non-cacheable accesses are used, the associated addresses must be legal according to the
UltraSPARC-II i physical address map (refer to the “USPIIi-1v Software Manual).
4.1.3 SME Advanced PCI Bridge (APB)
The SME Advanced PCI Bridge (SME: SME2411) interfaces directly with the UltraSPARC-II i
microprocessor and concentrates two (2), +5V, 32-bit, 33MHz PCI buses into one +3.3V, 32-bit, 66 MHz PCI
bus that interface directly with the UltraSPARC-II
i . The 66 MHz PCI-to-CPU can achieve a peak bandwidth
of 2 GBits/sec. Within the USPII i -1v, the two (2), 33 MHz PCI busses are referred to as PCIA and PCIB.
4.1.4 SME Reset, Interrupt, and Clock (RIC)
The SME Reset, Interrupt and Clock (SME: STP2210QFP) ASIC provides a variety of functions on the
USPII
i -1v. The RIC manages system resets, system interrupts, system scans, and system clock control
functions. These functions are divided into independent functional blocks on the RIC.
The interrupt controller on the RIC accepts all interrupts from the USPII i -1v subsystems (up to 41 interrupts)
and delivers encoded interrupts on the six (6) interrupt lines routed to the UltraSPARC-II i microprocessor.
Interrupts are accepted by the RIC in a round-robin priority scheme. The interrupts received by the RIC are
not passed to the UltraSPARC-II
i in the order they are received. Instead, a priority level is assigned. Eight (8)
interrupt levels are implemented in hardware. For more information concerning the SME RIC ASIC, refer to
Chapter 7, "Resets."
4.1.5 Tundra Universe IIB
The Tundra Universe IIB (Tundra: CA91C142) ASIC interfaces the local 32-bit PCI bus to the VMEbus. The
Universe IIB includes a 33 MHz, 32-bit PCI bus interface, a fully compliant, high performance, 64-bit
VMEbus interface as well as a broad range of VMEbus address and data transfer modes of:
• A32/A24/A16 master and slave transfer, except for A64 and A40
• D64/D32/D16/D08 master and slave transfer, except for MD32
• MBLT, BLT, ADOH, RMW, LOCK, and location monitors
The Universe IIB also includes support for full VMEbus System Controller, nine user programmable slave
images, and seven interrupt lines. For more information on the Universe IIB, refer to Chapter 5, "Universe-
IIB Description." and the
Tundra Universe II User Manual , published by Tundra (Tundra Document Number
8091142.MD300.01).