Themis USPIIi-1v, Hardware Manual

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USPIIi-1v Hardware Manual
5-10
Themis Computer
5.4.2.1 PCI Bus Fields
Decoding for VMEbus accesses is based on the address and command information produced by a PCI bus
master. The PCI Target Interface claims a cycle if there is an address match and if the command matches
certain criteria.
The PCI target images are A32-capable only. For accesses other than A32 the Special PCI Target Image may
be used (refer to Section 5.4.2.4, "Special PCI Target Image," on page 5-11). Of the eight standard PCI target
images, the first and fifth (PCI target images 0 and 4) have a 4 KB resolution. PCI target images 1 to 3 and 5
to 8 have a 64 KB resolution.
Warning —
!
The address space of a VMEbus slave image must not overlap with the address space for the
Universe II’s control and status registers.
5.4.2.2 VMEbus Fields
The VMEbus fields cause the Universe II to generate the appropriate VMEbus address, AM code, and cycle
type, allowing PCI transactions to be mapped to a VMEbus transaction. It is possible to use invalid
combinations, such as block transfers in A16 space. This may cause illegal transactions on the VMEbus. All
accesses beyond the 4 GB limit will wrap around to the low address range
.
Figure 5-3. Address Translation for PCI Bus to VMEbus Transfers
Table 5-9. PCI Bus Fields for PCI Bus Target Image
Field Register Bits Description
base BS[31:12] or BS[31:16] in LSIx_BS Multiples of 4 or 64 KBytes (base to
bound: maximum of 4 GB)
bound BD[31:12] or BD[31:16] in LSIx_BD
address space LAS in LSIx_CTL Memory or I/O
A32 Image
Offset [31..12]
VME [31..12] VME[11..0]
+
PCI [11..0] PCI [31..12]