Themis USPIIi-1v, Hardware Manual

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Themis Computer
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5. Universe-IIB Description
Figure 5-2. Address Translation for VMEbus to PCI Bus Transfers
5.4.1.3 Control Fields
A VMEbus slave image is enabled using the EN bit of the control field. The control field also specifies how
reads and writes are processed: either as a coupled transfer or a posted write. At power up, all images are
disabled and configured for coupled reads and writes.
Note — For a VMEbus slave image to respond to an incoming cycle, the PCI Master Interface must be
enabled (bit BM in the PCI_CSR register).
5.4.2 PCI Bus Target Images
The Universe II accepts accesses from the PCI bus with specific programmed PCI target images that open
windows to the VMEbus and control to the type of access to the VMEbus. There are eight (0-7) standard PCI
target images and one special PCI target image. The special PCI target image may be used for A16 and A24
transaction, freeing the other 8 images for standard A32 transactions.
Address space LAS in VSIx_CTL Memory, I/O, Configuration
RMW LLRMW in VSIx_CTL RMW enable bit
Table 5-8. Control Fields for VMEbus Slave Image
Field Register Bits Description
image enable EN in VSIx_CTL enable bit
posted write PWEN in VSIx_CTL posted write enable bit
prefetched read PREN in VSIx_CTL prefetched read enable bit
enable PCI64 LD64EN in VSIx_CTL enables 64-bit PIC bus transactions
Table 5-7. PCI Bus Fields for VMEbus Slave Image
Field Register Bits Description
A32 Image
Offset [31..12]
VME [31..12] VME[11..0]
+
PCI [11..0] PCI [31..12]