Themis USPIIi-1v, Hardware Manual

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Themis Computer
6-1
6
6 FPGA, Watchdog, Voltage and Temperature Sensors
6.1 FPGA
6.1.1 Introduction
The FPGA device on the USPII i -1v is the Altera EPF882 and resides on the EBus2 of the baseboard PCI I/O
ASICs. Physically, the FPGA is located on the baseboard. The FPGA implements a voltage monitor, boot
address decoder, a three-level watchdog timer, and the READY_LED register. At boot-up the FPGA self
loads from a serial EPROM (Altera EPC1213PC8) to program itself for these features.
Full description of the FPGA registers is presented in the “USPIIi-1v Software Manual”.
6.1.2 Boot Address Decoder
The Flash EPROM logic is made of 3 Flash devices:
• System Flash (2MB or 4 MB) is loaded at factory with OpenBoot for the Sun Configuration
• User Flash 1 (4 MB) is loaded at factory with OpenBoot for the PS/2 Configuration
• User Flash 2 (4 MB) is not loaded
Depending on the board configuration, either System Flash/User Flash 2 (in PS/2 Configuration) or User
Flash 1/User Flash 2 (in Sun configuration) will be available for user programs or data. The USPIIi-1v
OpenBoot contain special commands to program Flash devices, please refer to the USPIIi-1v Software
Manual.