Themis USPIIi-1v, Hardware Manual

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USPIIi-1v Hardware Manual
5-12
Themis Computer
The 64 MB space is divided into four (4), 16 MB spaces that are selected using AD[25:16]. For each region,
the upper 64 KB map to VMEbus A16 space, while the remaining portion map to VMEbus A24 space. The
addressing of this slave image is depicted in
Figure 5-2 "Address Translation for VMEbus to PCI Bus
Transfers," on page 5-9.
.
The special PCI target image register is described below.
Table 5-12. PCI Bus Fields for Special PCI Bus Target Image
Field Register Bits Description
base BS[05] in 64 MB aligned base address for the
image
address space LAS in Places Image in Memory or I/O
Table 5-13. PCI Bus Fields for Special PCI Bus Target Image
Field Register Bits Description
maximum data width VDW in separately set each region for 16 or
32 bits
mode SUPER in separately set each region for
supervisor or non-privileged
type PGM in Program or data
cycle VCT in Separately sets each region as pro-
gram or data
Table 5-14. Control Fields for Special PCI Bus Target Image
Field Register Bits Description
image enable EN in enable bit
posted write PWEN in posted write enable bit
Table 5-15. Special PCI Target Image Register (Offset 188)
Bits Name Type Reset
State
Description
31 EN R/W 0 Image Enable
0 = Disable, 1 = Enable
30 PWEN R/W 0 Posted Write Enable
0 = Disable, 1 = Enable
29:24 Reserved
23:20 VDW [3..0] R/W 0 VMEbus Maximum Datawidth. Each of the four bits specifies a
data width for the corresponding 16 MB regions. The lower order
bits correspond to the lower order address regions.
0 = 16 bit, 1 = 32 bit
19:16 Reserved