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Control Registers
Serial Peripheral Interface (SPI) Module (SPNU195E)
29
Bit 2
RCVR OVRN.
Receiver overrun flag.
This bit is a read/clear only flag. The SPI hardware sets this bit when an
operation completes before the previous character has been read from the
buffer. The bit indicates that the last received character has been overwritten
and therefore lost. The SPI will generate an interrupt request if this bit is set
and the OVRN INTEN bit (SPICTRL3.3) is set high.
This bit is cleared in one of four ways:
❏
Reading the SPIBUF register
❏
Writing a 1 to this bit
❏
Writing a 0 to SPIEN (SPICTRL2.4)
❏
System reset
0
=
Overrun condition did not occur
1
=
Overrun condition has occurred
Bit 1
RXINTEN.
An interrupt is to be generated when the RXINTFLAG bit (SPICTRL3.0) is set
by hardware. Otherwise, no interrupt will be generated.
0
=
Interrupt will not be generated
1
=
Interrupt will be generated
Bit 0
RXINTFLAG.
Serves as the SPI interrupt flag.
This flag is set when a word is received and copied into the buffer register
(SPIBUF). If RXINTEN is enabled, an interrupt is also generated. During
emulation mode, however, a read to the emulation register (SPIEMU) does
not clear this flag bit. This bit is cleared in one of four ways:
❏
Reading the SPIBUF register
❏
Writing a 1 to this bit
❏
Writing a 0 to SPIEN (SPICTRL2.4)
❏
System reset
0
=
Interrupt condition did not occur
1
=
Interrupt condition did occur
Summary of Contents for TMS470R1 series
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