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Texas Instruments TMS470R1 series, Reference Manual

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SPI Operation Modes

Serial Peripheral Interface (SPI) Module (SPNU195E)

9

2.4

SPI Operation; Five-Pin Option (Hardware Handshaking)

To use the hardware handshaking mechanism, both the SPIENA pin and
SPISCS pin must be configured as functional pins. 

In the master SPI (CLKMOD = 1), if the SPIENA pin is configured as a
functional input. If configured as a slave SPI, the SPIENA pin is configured as
a functional output. If the SPIENA pin is in high-z mode (ENABLE_HIGHZ =
1), the slave SPI will put this signal into the high-impedance state if it receives
a new character from the master or if the slave becomes de-selected by the
master (SPISCS goes high). The slave will drive the signal low when new
data is written to the slave shift register (SPIDAT0) and the slave has been
selected by the master (SPISCS is low).

If the SPIENA pin is in push-pull mode (ENABLE_HIGHZ = 0), the slave will
drive SPIENA high only if there is new data in the buffer register and the slave
is selected by the master (SPISCS is low). The slave SPI will drive the
SPIENA signal low when new data is written to the slave shift register
(SPIDAT0) and the slave is selected by the master (SPISCS is low). If the
slave is de-selected by the master (SPISCS goes high), the slave SPIENA
signal is driven low, allowing the master SPI to communicate with other slave
SPIs.

In the master SPI (CLKMOD = 1), the SPISCS pin is configured as a
functional output. If configured as a slave SPI (CLKMOD = 0), the SPISCS
pin is configured as a functional input. A write to the master’s SPIDAT1 shift
register will automatically drive the SPISCS signal low. The master will drive
the SPISCS signal high again after transmitting the new character. If the new
data is written to the master’s SPIDAT0 shift register, the SPISCS signal will
NOT be driven low.

Summary of Contents for TMS470R1 series

Page 1: ...TMS470R1x Serial Peripheral Interface SPI Reference Guide Literature Number SPNU195E August 2005 ...

Page 2: ...tute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of information in TI data books or data sheets is permissible only if reproduction is...

Page 3: ...REVISION HISTORY REVISION DATE NOTES E 8 05 Page 16 Baud Rate Limitations section added Page 24 information on slave prescale baud rate added Page 27 note on clearing SPIBUF added ...

Page 4: ......

Page 5: ... 5 DMA Interface 19 6 Control Registers 20 6 1 SPI Control Register 1 SPICTRL1 24 6 2 SPI Control Register 2 SPICTRL2 26 6 3 SPI Control Register 3 SPICTRL3 28 6 4 SPI Shift Register 0 SPIDAT0 30 6 5 SPI Shift Register 1 SPIDAT1 31 6 6 SPI Buffer Register SPIBUF 32 6 7 SPI Emulation Register SPIEMU 34 6 8 SPI Pin Control Register 1 SPIPC1 35 6 9 SPI Pin Control Register 2 SPIPC2 37 6 10 SPI Pin Co...

Page 6: ... SPISCS 7 4 SPI Four Pin Option with SPIENA 8 5 SPI Five Pin Option with SPIENA and SPISCS 10 6 Clock Mode with POLARITY 0 and PHASE 0 13 7 Clock Mode with POLARITY 0 and PHASE 1 13 8 Clock Mode with POLARITY 1 and PHASE 0 14 9 Clock Mode with POLARITY 1 and PHASE 1 14 10 Five Bits per Character 5 Pin Option 15 ...

Page 7: ...nous serial peripheral interface SPI The SPI is in effect a programmable length shift register used for high speed communication between external peripherals or other microcontrollers 1 Overview 2 2 SPI Operation Modes 3 3 General Purpose I O 17 4 Low Power Mode 18 5 DMA Interface 19 6 Control Registers 20 Topic Page ...

Page 8: ...The pins SPIENA and SPISCS are optional and may be used if the pin are present on a given device The SPI has the following attributes 16 bit shift register Receive buffer register 8 bit baud clock generator Serial clock SPICLK I O pin Slave in master out SPISIMO I O pin Slave out master in SPISOMI I O pin SPI enable SPIENA I O pin 4 or 5 pin mode only Slave chip select SPISCS I O pin 4 or 5 pin mo...

Page 9: ...onnected to that signal Writing to SPIDAT0 will not drive SPISCS low thus allowing the master to communicate with all slave devices connected to the same SPI bus In addition a handshaking mechanism provided by the SPIENA pin enables the slave to delay the generation of the clock signal supplied by the master as long as it is not prepared for the next exchange of data Figure 1 SPI Module Block Diag...

Page 10: ...hift register used in automatic slave chip select mode only 31 0x14 SPIBUF SPI Buffer Register Holds received word 32 0x18 SPIEMU SPI Emulation Register Mirror of SPIBUF Read does not clear flags 34 0x1C SPIPC1 SPI Pin Control Register 1 Controls the direction of data on the I O pins 35 0x20 SPIPC2 SPI Pin Control Register 2 Reflects the values on the I O pins 37 0x24 SPIPC3 SPI Pin Control Regist...

Page 11: ...t LSB of the SPIDAT0 register When the selected number of bits has been transmitted the data is transferred to the SPIBUF register for the CPU to read Data is stored right justified in SPIBUF When the specified number of bits has been shifted through the SPIDAT0 register the following events occur The RXINTFLAG bit SPICTRL3 0 is set to 1 The SPIDAT0 register contents transfer to the SPIBUF registe...

Page 12: ...egister is transmitted to the network when the SPICLK signal is received from the network master To receive data the SPI waits for the network master to send the SPICLK signal and then shifts data on the SPISIMO pin into the SPIDAT0 register If data is to be transmitted by the slave simultaneously it must be written to the SPIDAT0 register before the beginning of the SPICLK signal ...

Page 13: ...ansmission has completed If data is written to SPIDAT0 SPISCS remains high see Figure 3 Figure 3 SPI Four Pin Option with SPISCS To use the SPISCS as a chip select the slave SPISCS pin must be configured as SPI functional SPIPC6 4 1 In this mode an active low signal on the SPISCS pin will allow the slave SPI to transfer data to the serial data line An inactive high signal will put the slave SPI s ...

Page 14: ... z mode ENABLE_HIGHZ 1 the slave will put SPIENA into the high impedance once it receives a new character If the SPIENA pin is in push pull mode ENABLE_HIGHZ 0 the slave will drive SPIENA high once it receives a new character The slave will drive SPIENA low again after new data is written to the slave shift register SPIDAT0 Figure 4 SPI Four Pin Option with SPIENA SPI four pin option 2 Master Slav...

Page 15: ...ISCS is low If the SPIENA pin is in push pull mode ENABLE_HIGHZ 0 the slave will drive SPIENA high only if there is new data in the buffer register and the slave is selected by the master SPISCS is low The slave SPI will drive the SPIENA signal low when new data is written to the slave shift register SPIDAT0 and the slave is selected by the master SPISCS is low If the slave is de selected by the m...

Page 16: ... pin option Master Slave Master 1 CLKMOD 1 Master 0 CLKMOD 0 SPIDAT1 SPIDAT0 MSB LSB MSB LSB Write to SPIDAT1 SPISOMI SPISIMO SPISOMI SPISIMO SPICLK SPICLK SPISCS SPISCS Write to SPIDAT0 Write to SPIDAT0 SLAVE Write to SPIDAT1 MASTER SPICLK SPISIMO SPISOMI SPIENA SPIENA SPIENA SPISCS ...

Page 17: ...word right justified plus any bits that are left over from previous transmissions that have been shifted to the left The diagram below shows how a 14 bit word is stored in the buffer once it is received In transmit mode the SPIBUF register contains the most recently transmit ted word left justified The diagram below shows how a 14 bit word needs to be written to the buffer in order to be transmitt...

Page 18: ... of SPICLK corresponding to each mode Having four signal options allows the SPI to interface with different types of serial devices Also shown are the SPICLK control bit polarity and phase values corresponding to each signal POLARITY PHASE ACTION 0 0 Data is output on the rising edge of SPICLK Input data is latched on the falling edge 0 1 Data is output one half cycle before the first rising edge ...

Page 19: ...SPICLK without delay Data is output on the rising edge of SPICLK Input data is latched on the falling edge of SPICLK A write to the SPIDAT register starts SPICLK 1 2 3 4 5 6 7 8 Clock polarity 0 Clock phase 1 Write SPIDAT SPICLK SPISIMO SPISOMI Sample in reception MSB D6 D5 D4 D3 D2 D1 LSB D6 D5 D4 D3 D2 D1 D7 1 2 3 4 5 6 7 8 D0 Clock phase 1 SPICLK with delay Data is output one half cycle before ...

Page 20: ...t delay Data is output on the falling edge of SPICLK A write to the SPIDAT register starts SPICLK Input data is latched on the rising edge of SPICLK Clock polarity 1 Clock phase 1 Write SPIDAT SPICLK SPISIMO SPISOMI Sample in reception MSB D6 D5 D4 D3 D2 D1 D0 LSB D6 D5 D4 D3 D2 D1 D7 Clock phase 1 SPICLK with delay Data is output one half cycle before the first falling edge of SPICLK and on the s...

Page 21: ...evices using a character length of five bits Figure 10 Five Bits per Character 5 Pin Option 7 6 5 4 3 7 6 3 4 5 7 6 5 4 3 7 6 3 4 5 Master SPI Int flag Slave SPI Int flag SPISOMI from slave SPISIMO from master Clock polarity 1 Clock phase 1 SPISCS SPICLK signal options K B SPIENA Clock polarity 1 Clock phase 0 Clock polarity 0 Clock phase 1 Clock polarity 0 Clock phase 0 ...

Page 22: ...SPICLK Doing so may allow the master to start a new SPI transmission before the slave is ready When operating with PHASE 0 the slave SPICLK must not be more than 1 faster than the master SPICLK When operating with PHASE 1 the slave SPICLK must not be more than two times faster than the master SPICLK If the slave SPICLK exceeds the master SPICLK by more than 1 when PHASE 0 or by 2x when PHASE 1 the...

Page 23: ...al output pins The direction is controlled in the SPIPC1 register Note that each pin can be programmed to be either a SPI pin or a GPIO pin through register SPIPC6 If the SPI function is to be used application software must ensure that each pin is configured as a SPI pin and not a GPIO pin or else unexpected behavior may result Note Unused SPI Pins If there are four or five SPI pins available and ...

Page 24: ...can be written to or read from any register A local low power mode has the same effect when both the local POWERDOWN bit and the system level PPWNOVR bit are set If only the local POWERDOWN bit is set then the SPI logic is not clocked but the registers continue to be clocked Since entering a low power mode has the effect of suspending all state machine activities care must be taken when entering s...

Page 25: ... a character is being transmitted or received the SPI will signal the DMA via a DMA request signal The DMA controller will then perform the needed data manipulation For DMA based transmissions all characters are assembled in RAM and DMA transfers move the message word by word from RAM into the SPIDAT0 register See the DMA controller specification Data is then read from SPIBUF clearing RXINTFLAG SP...

Page 26: ...Control Registers 20 6 Control Registers This section describes the SPI control data and pin registers The registers support 16 bit and 32 bit writes ...

Page 27: ...5 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 0x00 SPICTRL1 Reserved Reserved PRESCALE 7 0 CHARLEN 4 0 0x04 SPICTRL2 Reserved Reserved CLK MOD SPI EN MASTER POWER DOWN POLAR ITY PHASE 0x08 SPICRTL3 Reserved Reserved ENABLE HIGHZ DMA REQ EN OVRN INTEN RCVR OVRN RXINT EN RXINT FLAG 0x0C SPIDAT0 Reserved SPIDAT0 15 0 0x10 SPIDAT1 Reserved SPIDAT1 15 0 ...

Page 28: ...0x18 SPIEMU Reserved SPIEMU 15 0 0x1C SPIPC1 Reserved Reserved SCS DIR SOMI DIR SIMO DIR CLK DIR ENABLE DIR 0x20 SPIPC2 Reserved Reserved SCS DIN SOMI DIN SIMO DIN CLK DIN ENABLE DIN 0x24 SPIPC3 Reserved Reserved SCS DOUT SOMI DOUT SIMO DOUT CLK DOUT ENABLE DOUT 0x28 SPIPC4 Reserved Reserved SCS DOUT SET SOMI DOUT SET SIMO DOUT SET CLK DOUT SET ENABLE DOUT SET Table 4 SPI Registers Continued ...

Page 29: ... a 32 bit register Two bits in the upper 16 bits are used for control all 16 lower bits are data buffers Offset Address Register 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 0x2C SPIPC5 Reserved Reserved SCS DOUT CLR SOMI DOUT CLR SIMO DOUT CLR CLK DOUT CLR ENABLE DIR 0x30 SPIPC6 Reserved Reserved SCS FUN SOMI FUN SIMO FUN CLK FUN ENABLE FUN Table 4 SPI Reg...

Page 30: ...for PRESCALE 1 to 255 SPI Baud Rate for PRESCALE 0 If the SPI is a network slave the module receives a clock signal on the SPICLK pin from the network master However the slave s PRESCALE baud rate Slave SPICLK must also conform to the following specifications Bits 31 16 0x00 Reserved U Bits 15 13 12 5 4 0 Reserved PRESCALE CHARLEN U RW 0 RW 0 R Read W Write U Undefined n Value after reset POLARITY...

Page 31: ...The binary value of the bit length must be programmed into this register Legal values are 0x03 to 0x10 Illegal values such as 0x00 or 0x1F are not detected and their effect is indeterminate Note CHARLEN Bits Must Be Initialized CHARLEN 4 0 must be initialized to the desired character length before the SPIEN bit is set Otherwise the first character may be shifted with an incorrect length ...

Page 32: ...s bit This bit must be set to 1 after all other SPI configuration bits have been written This prevents an invalid operation of the SPI while the clock polarity is being changed When this bit is 0 the SPI shift registers SPIDAT0 and SPIDAT1 are held in reset mode and forced to 0x0000 The RXINTFLAG SPICTRL3 0 and RCVROVRN SPITRL3 2 bits are also held in reset mode and forced to 0 when this bit is 0 ...

Page 33: ...own state 0 SPI in active mode 1 SPI in powerdown mode Bit 1 POLARITY Controls the polarity of the SPICLK Clock polarity and clock phase SPICTRL2 0 controls four clocking schemes on the SPICLK pin See Figure 6 to Figure 9 page 13 for wave form diagrams of the SPI clocking schemes Bit 0 PHASE Data is sent or latched in phase with the clock signal When PHASE 1 SPICLK is delayed by one half cycle fro...

Page 34: ...pin is in high z Bit 4 DMA REQ EN DMA request enable Enables the DMA request signal to be generated for both receive and transmit channels 0 DMA is not used 1 DMA is used Bit 3 OVRNINTEN Overrun interrupt enable An interrupt is to be generated when the RCVR OVRN flag bit SPICTRL3 2 is set by hardware Otherwise no interrupt will be generated 0 Overrun interrupt will not be generated 1 Overrun inter...

Page 35: ...RL2 4 System reset 0 Overrun condition did not occur 1 Overrun condition has occurred Bit 1 RXINTEN An interrupt is to be generated when the RXINTFLAG bit SPICTRL3 0 is set by hardware Otherwise no interrupt will be generated 0 Interrupt will not be generated 1 Interrupt will be generated Bit 0 RXINTFLAG Serves as the SPI interrupt flag This flag is set when a word is received and copied into the ...

Page 36: ...fted into the SPIDAT0 register When transmitting data input data is automatically clocked in at the receive side As the data is shifted from the MSB the LSB of the received data is shifted in Similarly when the shift register is used as a receiver the shift register continues to send data out as it receives new data on each input clock cycle This allows the concurrent transmission and reception of...

Page 37: ...N register forces the lower 16 bits of the SPIDAT1 register to 0x00 Write to this register ONLY when using the automatic Slave Chip Select feature See section 2 SPI Operation Modes on page 3 A write to this register will drive the SPISCS signal low When data is read from this register the value is indeterminate because of the shift operation The value in the buffer register SPIBUF should be read a...

Page 38: ...ime This bit is cleared in one of four ways Reading the SPIBUF register Writing a 1 to this bit Writing a 0 to SPIEN SPICTRL2 4 System reset 0 Overrun condition did not occur 1 Overrun condition has occurred Note The SPIBUF Register The SPIBUF is a 32 bit register Two bits in the upper 16 bits are used for control all 16 lower bits are data buffers Bits 31 18 17 16 0x14 Reserved RCVR OVRN IMG INT ...

Page 39: ...System reset 0 Interrupt condition did not occur 1 Interrupt condition did occur Bits 15 0 SPIBUF SPI buffer The data in this register is the data transferred from the shift register SPIDAT Since the data is shifted into the SPI most significant bit first for word lengths less than 16 the data is stored right justified in the register Note SPI Buffer Reading the SPIBUF register clears the RCVROVRN...

Page 40: ...effect Bits 15 0 SPIEMU SPI emulation SPI emulation is a mirror of the SPIBUF register The only difference between SPIEMU and SPIBUF is that a read from SPIEMU does not clear the RCVR OVRN SPICTRL3 2 or RXINTFLAG SPICTRL3 0 bits Bits 31 16 0x18 Reserved U Bits 15 0 SPIEMU R U R Read U Undefined n Value after reset ...

Page 41: ...direction of the SPISOMI pin when it is used as a general purpose I O pin If the SPISOMI pin is used as a SPI functional pin the I O direction is determined by the MASTER bit SPICTRL2 3 0 SPISOMI pin is an input 1 SPISOMI pin is an output Bit 2 SIMODIR SPISIMO direction Controls the direction of the SPISIMO pin when it is used as a general purpose I O pin If the SPISIMO pin is used as a SPI functi...

Page 42: ...on is determined by the CLKMOD bit SPICTRL2 5 0 SPICLK pin is an input 1 SPICLK pin is an output Bit 0 ENA DIR SPIENA direction Controls the direction of the SPIENA pin when it is used as a general purpose I O If the SPIENA pin is used as a functional pin then the I O direction is determined by the CLKMOD bit SPICTRL2 5 0 SPIENA pin is an input 1 SPIENA pin is an output ...

Page 43: ...the value of the SPISOMI pin 0 Current value on SPISOMI pin is logic 0 1 Current value on SPISOMI pin is logic 1 Bit 2 SIMO DIN SPISIMO data in Reflects the value of the SPISIMO pin 0 Current value on SPISIMO pin is logic 0 1 Current value on SPISIMO pin is logic 1 Bit 1 CLK DIN Clock data in Reflects the value of the SPICLK pin 0 Current value on SPICLK pin is logic 0 1 Current value on SPICLK pi...

Page 44: ...Control Registers 38 Bit 0 ENA DIN SPIENA data in Reflects the value of the SPIENA pin 0 Current value on SPIENA pin is logic 0 1 Current value on SPIENA pin is logic 1 ...

Page 45: ...ve when the SPISOMI pin is configured as a general purpose I O pin and configured as an output pin The value of this bit indicates the value sent to the pin 0 Current value on SPISOMI pin is logic 0 1 Current value on SPISOMI pin is logic 1 Bit 2 SIMO DOUT SPISIMO dataout write Only active when the SPISIMO pin is configured as a general purpose I O pin and configured as an output pin The value of ...

Page 46: ...tes the value sent to the pin 0 Current value on SPICLK pin is logic 0 1 Current value on SPICLK pin is logic 1 Bit 0 ENA DOUT SPIENA dataout write Only active when the SPIENA pin is configured as a general purpose I O pin and configured as an output pin The value of this bit indicates the value sent to the pin 0 Current value on SPIENA pin is logic 0 1 Current value on SPIENA pin is logic 1 ...

Page 47: ...ISCS pin Read 0 Current value on SPISCS pin is logic 0 1 Current value on SPISCS pin is logic 1 Bit 3 SOMI DSET SPISOMI dataout set Only active when the SPISOMI pin is configured as a general purpose output pin A value of one written to this bit sets the corresponding SPISOMIDOUT bit SPIPC3 3 to one Write 0 Has no effect 1 Logic 1 placed on SPISOMI pin Read 0 Current value on SPISOMI pin is logic ...

Page 48: ...utput pin A value of one written to this bit sets the corresponding CLKDOUT bit SPIPC3 1 to one Write 0 Has no effect 1 Logic 1 placed on SPICLK pin Read 0 Current value on SPICLK pin is logic 0 1 Current value on SPICLK pin is logic 1 Bit 0 ENA DSET SPIENA dataout set Only active when the SPIENA pin is configured as a general purpose output pin A value of one written to this bit sets the correspo...

Page 49: ...CS pin Read 0 Current value on SPISCS pin is logic 0 1 Current value on SPISCS pin is logic 1 Bit 3 SOMI DCLR SPISOMI dataout clear Only active when the SPISOMI pin is configured as a general purpose output pin A value of one written to this bit clears the corresponding SPISOMIDOUT bit SPIPC3 3 to zero Write 0 Has no effect 1 Logic 0 placed on SPISOMI pin Read 0 Current value on SPISOMI pin is log...

Page 50: ...utput pin A value of one written to this bit clears the corresponding CLKDOUT bit SPIPC3 1 to zero Write 0 Has no effect 1 Logic 0 placed on SPICLK pin Read 0 Current value on SPICLK pin is logic 0 1 Current value on SPICLK pin is logic 1 Bit 0 ENA DCLR SPIENA dataout clear Only active when the SPIENA pin is configured as a general purpose output pin A value of one written to this bit clears the c...

Page 51: ...function Determines whether the SPISOMI pin is to be used as a general purpose I O pin or as a SPI functional pin 0 SPISOMI pin is a GPIO 1 SPISOMI pin is a SPI functional pin Bit 2 SIMO FUN Slave in master out function Determines whether the SPISIMO pin is to be used as a general purpose I O pin or as a SPI functional pin 0 SPISIMO pin is a GPIO 1 SPISIMO pin is a SPI functional pin Bit 1 CLK FUN...

Page 52: ...l Registers 46 Bit 0 ENA FUN SPIENA function Determines whether the SPIENA pin is to be used as a general purpose I O pin or as a SPI functional pin 0 SPIENA pin is a GPIO 1 SPIENA pin is a SPI functional pin ...

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