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Control Registers
Serial Peripheral Interface (SPI) Module (SPNU195E)
35
6.8
SPI Pin Control Register 1 (SPIPC1)
Bits 31:5
Reserved.
Reads are undefined and writes have no effect
Bit 4
SCS DIR: SPISCS direction.
Controls the direction of the SPISCS pin when it is used as a general-purpose
I/O pin. If the SPISCS is used as a SPI functional pin, the I/O direction is
determined by the CLKMOD bit (SPICTRL2.5).
0
=
SPISCS pin is an input
1
=
SPISCS pin is an output
Bit 3
SOMI DIR: SPISOMI direction.
Controls the direction of the SPISOMI pin when it is used as a general-
purpose I/O pin. If the SPISOMI pin is used as a SPI functional pin, the I/O
direction is determined by the MASTER bit (SPICTRL2.3).
0
=
SPISOMI pin is an input
1
=
SPISOMI pin is an output
Bit 2
SIMODIR: SPISIMO direction.
Controls the direction of the SPISIMO pin when it is used as a general-
purpose I/O pin. If the SPISIMO pin is used as a SPI functional pin, the I/O
direction is determined by the MASTER bit (SPICTRL2.3).
0
=
SPISIMO pin is an input
1
=
SPISIMO pin is an output
Bits
31
16
0x1C
Reserved
U
Bits
15
5
4
3
2
1
0
Reserved
SCS
DIR
SOMI
DIR
SIMOI
DIR
CLK
DIR
ENA
DIR
U
RW-0
RW-0
RW-0
RW-0
RW-0
R = Read, C = Clear, U = Undefined;
-n =
Value after reset
Summary of Contents for TMS470R1 series
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