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Control Registers
30
6.4
SPI Shift Register 0 (SPIDAT0)
Bits 31:16
Reserved
Reads are undefined and writes have no effect.
Bits 15:0
SPIDAT0 SPI shift data 0.
These bits make up the SPI shift register 0. Data is shifted out of the MSB (bit
15) and into the LSB (bit 0).
SPIEN (SPICTRL2.4) must be set to 1 before this register can be written to.
Writing a 0 to the SPIEN register forces the lower 16 bits of the SPIDAT0
register to 0x00.
When data is read from this register, the value is indeterminate because of
the shift operation. The value in the buffer register (SPIBUF) should be read
after the shift operation is complete to determine what data was shifted into
the SPIDAT0 register.
When transmitting data, input data is automatically clocked in at the receive
side. As the data is shifted from the MSB, the LSB of the received data is
shifted in. Similarly, when the shift register is used as a receiver, the shift
register continues to send data out as it receives new data on each input
clock cycle. This allows the concurrent transmission and reception of data.
The application software must determine whether the data transferred is
valid.
For word sizes of 8 bits or less (as determined by CHARLEN)
(SPICTRL1.4:0), the shift register is tapped at SPIDAT.7. As a result, data of
8 bits does not need to be justified at all. For data of less than 8 bits, the data
should be justified as if it is an 8-bit register.
Bits
31
16
0x0C
Reserved
U
Bits
15
0
SPIDAT0
RW-0
R = Read, W = Write, U = Undefined;
-n =
Value after reset
Summary of Contents for TMS470R1 series
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