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Control Registers
24
6.1
SPI Control Register 1 (SPICTRL1)
Bits 31:13
Reserved.
Reads are undefined and writes have no effect.
Bits 12:5
PRESCALE
Determines the bit transfer rate if the SPI is the network master.
There are 255 data transfer rates (each a function of the interface clock) that
can be selected. One data bit is shifted per SPICLK cycle.
SPI Baud Rate for PRESCALE = 1 to 255
SPI Baud Rate for PRESCALE = 0
If the SPI is a network slave, the module receives a clock signal on the
SPICLK pin from the network master. However, the slave’s PRESCALE baud
rate (Slave SPICLK) must also conform to the following specifications:
Bits
31
16
0x00
Reserved
U
Bits
15
13
12
5
4
0
Reserved
PRESCALE
CHARLEN
U
RW-0
RW-0
R = Read, W = Write, U = Undefined;
-n =
Value after reset
POLARITY
PHASE
SPICLK RATIO
X
0
%)
X
1
SPIBaudRate
ICLK
PRESCALE
1
+
(
)
-------------------------------------------------
=
SPIBaudRate
ICLK
2
--------------
=
MasterSPICLK
2
-------------------------------------------
SlaveSPICLK
MasterSPICLK
1
+
(
)
≤
≤
MasterSPICLK
2
-------------------------------------------
SlaveSPICLK
MasterSPICLK
2
×
(
)
≤
≤
Summary of Contents for TMS470R1 series
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