SPI Operation Modes
12
2.6
Clocking Modes
There are four clock modes in which SPICLK may operate, depending on the
choice of the phase (delay/no delay) and the polarity (rising edge / falling
edge) of the clock. When operating with PHASE active, the SPI makes the
first bit of data available after the SPIDAT0 register is written and before the
first edge of SPICLK. The data input and output edges depend on the values
of both POLARITY and PHASE as shown in
Table 2
.
Table 2.
Clocking Modes
Figure 6
to
Figure 9
illustrate the four possible signals of SPICLK
corresponding to each mode. Having four signal options allows the SPI to
interface with different types of serial devices. Also shown are the SPICLK
control bit polarity and phase values corresponding to each signal.
POLARITY
PHASE
ACTION
0
0
Data is output on the rising edge of SPICLK. Input
data is latched on the falling edge.
0
1
Data is output one half-cycle before the first rising
edge of SPICLK and on subsequent falling edges.
Input data is latched on the rising edge of SPICLK.
1
0
Data is output on the falling edge of SPICLK. Input
data is latched on the rising edge.
1
1
Data is output one half-cycle before the first falling
edge of SPICLK and on subsequent rising edges.
Input data is latched on the falling edge of SPICLK.
Summary of Contents for TMS470R1 series
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