Serial Ports
12-27
Peripherals
Table 12–5. Receive/Transmit Timer-Control Register Register Bits Summary (Continued)
Abbreviation
Function
Name
Reset
Value
RCLKSRC
0
Receive timer clock
source
Specifies the source of the receive timer clock.
When RCLKSRC = 1, an internal clock with frequency equal
to one-half the CLKOUT frequency is used to increment the
counter.
When RCLKSRC = 0, you can use an external signal from
the CLKR pin to increment the counter. The external clock
source is synchronized internally, allowing for external
asynchronous clock sources that do not exceed the speci-
fied maximum allowable external clock frequency (that is,
less than f(H1)/2.6).
RTSTAT
0
Receive timer status
Indicates the status of the receive timer. It tracks what would
be the output of the uninverted CLKR pin.
This flag sets a CPU interrupt on a transition from 0 to 1. A
write has no effect.
12.2.5 Receive/Transmit Timer-Counter Register
The receive/transmit timer-counter register is a 32-bit register (see
Figure 12–17). Bits 15–0 are the transmit timer-counter, and bits 31 – 16 are
the receive timer-counter. Each counter is cleared to 0 whenever it increments
to the value of the period register (see Section 12.2.6).
It is also set to 0 at reset.
Figure 12–17. Receive/Transmit Timer-Counter Register
31
16
15
0
Receive counter
Transmit counter
Note:
All bits are read/write.
