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Texas Instruments TMS320C3x, User Manual

The Texas Instruments TMS320C3x, known for its exceptional performance and versatility, heralds a new era in signal processing technology. Unlock the full potential of this remarkable product by accessing the comprehensive User Manual that can be easily downloaded for free from manualshive.com.

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Condition Codes and Flags

13-31

Assembly Language Instructions

Table 13–12. Condition Codes and Flags (Continued)

(d) Compare to zero

Condition

Code

Description

Flag

†

Z
NZ
P
N
NN

00101
00110
01001
00111
01010

Zero
Not zero
Positive
Negative
Non-negative

Z

∼

Z

∼

N AND 

∼

Z

N

∼

N

(e) Compare to condition flags

Condition

Code

Description

Flag

†

NN
N
NZ
Z
NV
V
NUF
UF
NC
C
NLV
LV
NLUF
LUF
ZUF

01010
00111
00110
00101
01100
01101
01110
01111
00100
00001
10000
10001
10010
10011
10100

Non-negative
Negative
Nonzero
Zero
No overflow
Overflow
No underflow
Underflow
No carry
Carry
No latched overflow
Latched overflow
No latched floating-point underflow
Latched floating-point underflow
Zero or floating-point underflow

∼

N

N

 

∼

Z

Z

 

∼

V

V

 

∼

UF

UF

 

∼

C

C

 

∼

LV

LV

 

∼

LUF

LUF

 

Z OR UF

 

†

∼

 = logical complement (not true condition)

Summary of Contents for TMS320C3x

Page 1: ...TMS320C3x User s Guide Literature Number SPRU031E 2558539 9761 revision L July 1997 Printed on Recycled Paper ...

Page 2: ...NED INTENDED AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE SUPPORT APPLICATIONS DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS Inclusion of TI products in such applications is understood to be fully at the risk of the customer Use of TI products in such applications requires the written approval of an appropriate TI officer Questions concerning potential risk applications should be dir...

Page 3: ...volved in many applications and gives the corresponding assembly language code for instructional purposes and for immediate use Whenever the detailed explanation of the underlying theory is too extensive to be included in this manual appropriate references are given for further information Notational Conventions This document uses the following conventions Program listings program examples and int...

Page 4: ...uction that has an optional parameter LALK 16 bit constant shift The LALK instruction has two parameters The first parameter 16 bit constant is required The second parameter shift is optional As this syntax shows if you use the optional second parameter you must precede it with a comma Square brackets are also used as part of the pathname specification for VMS pathnames in this case the brackets a...

Page 5: ...ions User s Guide literature number SPRU194 provides information to assist you in application development for the TMS320C3x generation of digital signal processors DSPs It includes example code and hardware connections for various appliances It also defines the principles involved in many applications and gives the corresponding assembly language code for instructional purposes and for immediate u...

Page 6: ...t serve the family of TMS320 digital signal processors A myriad of products and applications are offered software and hardware development tools speech recognition image processing noise can cellation modems etc References The publications in the following reference list contain useful information regarding functions operations and applications of digital signal processing DSP These books also pro...

Page 7: ...sing Software Ottawa Canada Carleton University 1983 Oppenheim Alan V Editor Applications of Digital Signal Processing Englewood Cliffs NJ Prentice Hall Inc 1978 Oppenheim Alan V and Schafer R W Digital Signal Processing Engle wood Cliffs NJ Prentice Hall Inc 1975 Oppenheim Alan V and Schafer R W Discrete Time Signal Processing Englewood Cliffs NJ Prentice Hall Inc 1989 Oppenheim Alan V and Willsk...

Page 8: ...ce Hall Inc 1983 Vaidyanathan P P Multirate Systems and Filter Banks Englewood Cliffs NJ Prentice Hall Inc Digital Control Theory Dote Y Servo Motor and Motion Control Using Digital Signal Processors Englewood Cliffs NJ Prentice Hall Inc 1990 Jacquot R Modern Digital Control Systems New York NY Marcel Dekker Inc 1981 Katz P Digital Control Using Microprocessors Englewood Cliffs NJ Prentice Hall In...

Page 9: ...J H Owsley N L Yen J L and Kak A C Array Signal Processing Englewood Cliffs NJ Prentice Hall Inc 1985 Hudson J E Adaptive Array Principles New York NY John Wiley and Sons 1981 Monzingo R A and Miller J W Introduction to Adaptive Arrays New York NY John Wiley and Sons 1980 ...

Page 10: ... Networking Hotline Fax 281 274 4027 Email TLANHOT micro ti com Europe Middle East Africa European Product Information Center EPIC Hotlines Multi Language Support 33 1 30 70 11 69 Fax 33 1 30 70 10 32 Email epic ti com Deutsch 49 8161 80 33 11 or 33 1 30 70 11 68 English 33 1 30 70 11 65 Francais 33 1 30 70 11 64 Italiano 33 1 30 70 11 67 EPIC Modem BBS 33 1 30 70 11 99 European Factory Repair 33 ...

Page 11: ... of the book Trademarks ABEL is a trademark of DATA I O CodeView MS MS DOS MS Windows and Presentation Manager are registered trademarks of Microsoft Corporation DEC Digital DX Ultrix VAX and VMS are trademarks of Digital Equipment Corporation HPGL is registered trademark of Hewlett Packard Company Macintosh and MPW are trademarks of Apple Computer Corp Micro Channel OS 2 PC DOS and PGA are tradem...

Page 12: ...2 2 Central Processing Unit CPU 2 6 2 2 1 Floating Point Integer Multiplier 2 8 2 2 2 Arithmetic Logic Unit ALU and Internal Buses 2 8 2 2 3 Auxiliary Register Arithmetic Units ARAUs 2 8 2 3 CPU Primary Register File 2 9 2 4 Other Registers 2 12 2 5 Memory Organization 2 13 2 5 1 RAM ROM and Cache 2 13 2 5 2 Memory Addressing Modes 2 17 2 6 Internal Bus Operation 2 18 2 7 External Memory Interface...

Page 13: ...ription of memory maps with explanation of instruction cache architecture algorithm and control bits 4 1 Memory 4 2 4 1 1 Memory Maps 4 2 4 1 2 Peripheral Bus Memory Map 4 9 4 2 Reset Interrupt Trap Vector Map 4 14 4 3 Instruction Cache 4 19 4 3 1 Instruction Cache Architecture 4 19 4 3 2 Instruction Cache Algorithm 4 21 4 3 3 Cache Control Bits 4 22 5 Data Formats and Floating Point Operation 5 1...

Page 14: ...on 5 43 5 11 Fast Logarithms on a Floating Point Device 5 44 5 11 1 Example of Fast Logarithm on a Floating Point Device 5 45 5 11 2 Points to Consider 5 47 6 Addressing Modes 6 1 Operation encoding and implementation of addressing modes format descriptions system stack management 6 1 Addressing Types 6 2 6 2 Register Addressing 6 3 6 3 Direct Addressing 6 4 6 4 Indirect Addressing 6 5 6 5 Immedia...

Page 15: ...Processing 7 33 7 6 7 CPU Interrupt Latency 7 35 7 6 8 External Interrupts 7 36 7 7 DMA Interrupts 7 38 7 7 1 DMA Interrupt Control Bits 7 38 7 7 2 DMA Interrupt Processing 7 39 7 7 3 CPU DMA Interaction 7 40 7 7 4 TMS320C3x Interrupt Considerations 7 41 7 7 5 TMS320C30 Interrupt Considerations 7 44 7 8 Traps 7 47 7 8 1 Initialization of Traps and Interrupts 7 47 7 8 2 Operation of Traps 7 47 7 9 ...

Page 16: ...nal interface timing diagrams programmable wait states and bank switching 10 1 TMS320C32 Memory Features 10 2 10 2 TMS320C32 Memory Overview 10 3 10 2 1 External Memory Interface Overview 10 3 10 2 2 Program Memory Access 10 4 10 2 3 Data Memory Access 10 5 10 3 Configuration 10 7 10 3 1 External Interface Control Registers 10 7 10 3 2 Using Physical Memory Width and Data Type Size Fields 10 13 10...

Page 17: ... Operation Modes 12 10 12 1 7 Using TCLKx as General Purpose I O Pins 12 12 12 1 8 Timer Interrupts 12 13 12 1 9 Timer Initialization Reconfiguration 12 13 12 2 Serial Ports 12 15 12 2 1 Serial Port Global Control Register 12 17 12 2 2 FSX DX CLKX Port Control Register 12 22 12 2 3 FSR DR CLKR Port Control Register 12 23 12 2 4 Receive Transmit Timer Control Register 12 25 12 2 5 Receive Transmit ...

Page 18: ...13 5 13 1 6 Interlocked Operations Instructions 13 5 13 1 7 Parallel Operations Instructions 13 6 13 1 8 Illegal Instructions 13 9 13 2 Instruction Set Summary 13 10 13 3 Parallel Instruction Set Summary 13 17 13 4 Group Addressing Mode Instruction Encoding 13 20 13 4 1 General Addressing Modes 13 20 13 4 2 3 Operand Addressing Modes 13 24 13 4 3 Parallel Addressing Modes 13 25 13 4 4 Conditional ...

Page 19: ... 7 TMS320C30 CPU Interrupt Flag IF Register 3 12 3 8 TMS320C31 CPU Interrupt Flag IF Register 3 12 3 9 TMS320C32 CPU Interrupt Flag IF Register 3 12 3 10 Effective Base Address of the Interrupt Trap Vector Table 3 14 3 11 Interrupt and Trap Vector Locations 3 15 3 12 I O Flag IOF Register 3 16 4 1 TMS320C30 Memory Maps 4 4 4 2 TMS320C31 Memory Maps 4 6 4 3 TMS320C32 Memory Maps 4 8 4 4 TMS320C30 P...

Page 20: ...Point Addition 5 33 5 18 Flowchart for NORM Instruction Operation 5 38 5 19 Flowchart for Floating Point Rounding by the RND Instruction 5 40 5 20 Flowchart for Floating Point to Integer Conversion by FIX Instruction 5 42 5 21 Flowchart for Integer to Floating Point Conversion by FLOAT Instruction 5 43 5 22 Tabulated Values for Mantissa 5 46 5 23 Fast Logarithm for FFT Displays 5 48 6 1 Direct Add...

Page 21: ...Use of Wait States for Write for M STRB 0 9 20 9 10 Read and Write for IOSTRB 0 9 21 9 11 Read With One Wait State for IOSTRB 0 9 22 9 12 Write With One Wait State for IOSTRB 0 9 23 9 13 Memory Read and I O Write for Expansion Bus 9 24 9 14 Memory Read and I O Read for Expansion Bus 9 25 9 15 Memory Write and I O Write for Expansion Bus 9 26 9 16 Memory Write and I O Read for Expansion Bus 9 27 9 ...

Page 22: ...al Diagram for 32 Bit Data Type Size and 8 Bit External Memory Width 10 36 10 22 RDY Timing for Memory Read 10 38 10 23 Read Read Write Sequence for STRBx Active 10 40 10 24 Write Write Read Sequence for STRBx Active 10 40 10 25 One Wait State Read Sequence for STRBx Active 10 41 10 26 One Wait State Write Sequence for STRBx Active 10 42 10 27 Zero Wait State Read and Write Sequence for IOSTRB Act...

Page 23: ...unter Register 12 27 12 18 Receive Transmit Timer Period Register 12 28 12 19 Transmit Buffer Shift Operation 12 28 12 20 Receive Buffer Shift Operation 12 29 12 21 Serial Port Clocking in I O Mode 12 30 12 22 Serial Port Clocking in Serial Port Mode 12 31 12 23 Data Word Format in Handshake Mode 12 33 12 24 Single 0 Sent as an Acknowledge Bit 12 33 12 25 Direct Connection Using Handshake Mode 12 ...

Page 24: ...stination Synchronization 12 67 12 47 DMA Timing When Destination is On Chip 12 69 12 48 DMA Timing When Destination is an STRB STRB0 STRB1 MSTRB Bus 12 70 12 49 DMA Timing When Destination is an IOSTRB Bus 12 72 13 1 Encoding for General Addressing Modes 13 21 13 2 Encoding for 3 Operand Addressing Modes 13 25 13 3 Encoding for Parallel Addressing Modes 13 25 13 4 Encoding for Extended Parallel A...

Page 25: ... 2 7 2 Interlocked Operations 7 13 7 3 TMS320C3x Pin Operation at Reset 7 21 7 4 Reset Interrupt and Trap Vector Locations for the TMS320C30 TMS320C31 Microprocessor Mode 7 27 7 5 Reset Interrupt and Trap Branch Locations for the TMS320C31 Microcomputer Boot Mode 7 28 7 6 Interrupt and Trap Vector Locations for the TMS320C32 7 30 7 7 Reset and Interrupt Vector Priorities 7 31 7 8 Interrupt Latency...

Page 26: ...ructure 11 8 11 3 Byte Wide Configured Memory 11 9 11 4 16 Bit Wide Configured Memory 11 10 11 5 32 Bit Wide Configured Memory 11 10 11 6 TMS320C31 Interrupt and Trap Memory Maps 11 12 11 7 Boot Loader Mode Selection 11 15 11 8 Source Data Stream Structure 11 21 12 1 Timer Global Control Register Bits Summary 12 5 12 2 Serial Port Global Control Register Bits Summary 12 18 12 3 FSX DX CLKX Port Co...

Page 27: ...dressing 6 4 6 2 Auxiliary Register Indirect 6 5 6 3 Indirect Addressing With Predisplacement Add 6 9 6 4 Indirect Addressing With Predisplacement Subtract 6 9 6 5 Indirect Addressing With Predisplacement Add and Modify 6 10 6 6 Indirect Addressing With Predisplacement Subtract and Modify 6 10 6 7 Indirect Addressing With Postdisplacement Add and Modify 6 11 6 8 Indirect Addressing With Postdispla...

Page 28: ...of XF Pin Configuration 7 20 7 14 Incorrect Use of Interlocked Instructions 7 20 7 15 Pending Interrupt 7 43 8 1 Standard Branch 8 5 8 2 Delayed Branch 8 6 8 3 Write to an AR Followed by an AR for Address Generation 8 7 8 4 A Read of ARs Followed by ARs for Address Generation 8 8 8 5 Program Wait Until CPU Data Access Completes 8 10 8 6 Program Wait Due to Multicycle Access 8 11 8 7 Multicycle Pro...

Page 29: ...ter Setup 2 12 43 12 6 CPU Transfer With Serial Port Transmit Polling Method 12 44 12 7 TMS320C3x Zero Glue Logic Interface to Burr Brown A D and D A 12 46 12 8 Array Initialization With DMA 12 75 12 9 DMA Transfer With Serial Port Receive Interrupt 12 76 12 10 DMA Transfer With Serial Port Transmit Interrupt 12 77 ...

Page 30: ... integration allows fast easy data movement and high speed numeric processing performance Extensive internal busing and a powerful DSP instruction set provide the devices with the speed and flexibility to execute at up to 60 million floating point operations per second MFLOPS The devices also feature a high degree of on chip parallelism that allows users to perform up to 11 operations in a single ...

Page 31: ...MA on the TMS320C32 supporting concurrent I O Short machine cycle time General purpose applications are greatly enhanced by the large address space multiprocessor interface internally and externally generated wait states two external interface ports one on the C31 and the C32 two timers two serial ports one on the C31 and the C32 and multiple interrupt structure The C3x supports a wide variety of ...

Page 32: ... 8 extended precision registers 8 auxiliary registers 2 index registers Address generation 0 Address generation 1 12 control registers 2 low power modes C31 C32 Controller RESET INT3 3 IACK XF1 0 H1 H3 MCBL MP X2 CLKIN VDD VSSSHZE MU6 0 X1 1 1 1 TMS320C3x Key Specifications The key specifications of the C3x devices include the following Performance up to 60 MFLOPS Highly efficient C language engin...

Page 33: ...They are enhanced versions of the C3x family and the lowest cost floating point processors on the market today These enhancements include a variable width memory inter face two channel DMA coprocessor with configurable priorities flexible boot loader and a relocatable interrupt vector table ...

Page 34: ...l 50 40 2K 4K 64 16M 32 8K 32 2 1 2 181 PGA 208 PQFP 0 to 85 commercial 27 75 2K Boot loader 64 16M 32 1 1 2 132 PQFP 0 to 85 commercial 55 to 125 military 33 60 2K Boot loader 64 16M 32 1 1 2 132 PQFP 0 to 85 commercial 40 to 125 extended 55 to 125 military C31 5 V 40 50 2K Boot loader 64 16M 32 1 1 2 132 PQFP 0 to 85 commercial 40 to 125 extended 55 to 125 military 50 40 2K Boot loader 64 16M 32...

Page 35: ... Cycle Time ns RAM ROM Cache Parallel Serial DMA Channels Timers Package Type Temperature 40 50 512 Boot loader 64 16M 32 16 8 1 2 2 144 PQFP 0 to 85 commercial 40 to 125 extended C32 5 V 50 40 512 Boot loader 64 16M 32 16 8 1 2 2 144 PQFP 0 to 85 commercial 40 to 125 extended 55 to 125 military 60 33 512 Boot loader 64 16M 32 16 8 1 2 2 144 PQFP 0 to 85 commercial ...

Page 36: ...Text to speech Neural networks Disk control Servo control Robot control Laser printer control Engine control Motor control Kalman filtering Secure communications Radar processing Sonar processing Image processing Navigation Missile guidance Radio frequency modems Sensor fusion Telecommunications Automotive Echo cancellation ADPCM transcoders Digital PBXs Line repeaters Channel multiplexing Modems ...

Page 37: ...access DMA of the C3x processor Topic Page 2 1 Overview 2 2 2 2 Central Processing Unit CPU 2 6 2 3 CPU Primary Register File 2 9 2 4 Other Registers 2 12 2 5 Memory Organization 2 13 2 6 Internal Bus Operation 2 18 2 7 External Memory Interface 2 19 2 8 Interrupts 2 21 2 9 Peripherals 2 22 2 10 Direct Memory Access DMA 2 24 2 11 TMS320C30 TMS320C31 and TMS320C32 Differences 2 26 Chapter 2 ...

Page 38: ... emphasize both hardware and software solu tions High performance is achieved through the precision and wide dynamic range of the floating point units large on chip memory a high degree of parallel ism and the DMA controller Figure 2 1 through Figure 2 3 show functional block diagrams of the C30 C31 and C32 architectures respectively ...

Page 39: ...rt 1 ÉÉÉ ÉÉÉ R Xtimer register ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉ Data transmit register Data receive register FSX1 DX1 CLKX1 FSR1 DR1 CLKR1 Timer0 Global control register Timer period register Timer counter register TCLK0 Timer1 Global control register Timer period register Timer counter register TCLK1 Port control Primary Expansion Transfer counter register PDATA bus PADDR bus DDATA bus DADDR1 bus DAD...

Page 40: ...gister Data transmit register Data receive register FSX0 DX0 CLKX0 FSR0 DR0 CLKR0 Timer0 Global control register Timer period register Timer counter register TCLK0 Timer1 Global control register Timer period register Timer counter register TCLK1 Port Control Primary STRB control register Transfer counter register PDATA bus DDATA bus DADDR1 bus DADDR2 bus DMADATA bus DMAADDR bus 24 40 32 32 24 24 3...

Page 41: ...X0 DX0 CLKX0 FSR0 DR0 CLKR0 TCLK0 Timer1 Timer period register TCLK1 PDATA bus PADDR bus DDATA bus DADDR1 bus DADDR2 bus DMADATA bus 40 32 24 24 24 24 32 32 32 CPU2 32 32 40 ÉÉÉÉÉ ÉÉÉÉÉ Receive transmit R X timer register Controller CPU1 REG1 REG2 DMAADDR bus STRB1 control reg IOSTRB control reg STRB1 IOSTRB STRB0 RESET INT 3 0 IACK XF 1 0 H1 H3 MCBL MP CLKIN CVSS 6 0 DVSS 6 0 IVSS 3 9 DVDD 11 3 V...

Page 42: ...ter based CPU architec ture The CPU consists of the following components Floating point integer multiplier Arithmetic logic unit ALU 32 bit barrel shifter Internal buses CPU1 CPU2 and REG1 REG2 Auxiliary register arithmetic units ARAUs CPU register file Figure 2 4 shows a diagram of the various CPU components ...

Page 43: ...sion registers R0 R7 Disp IR0 IR1 ARAU0 ARAU1 Auxiliary registers AR0 AR7 Other registers 12 32 32 40 40 40 40 40 40 40 32 24 24 32 32 32 32 24 24 32 32 BK 40 ALU DADDR1 bus DADDR2 bus DDATA bus CPU1 bus CPU2 bus REG1 bus REG2 bus REG1 bus CPU1 bus REG2 bus DADDR2 bus DADDR1 bus Disp an 8 bit integer displacement carried in a program control instruction ...

Page 44: ...ternal Buses The ALU performs single cycle operations on 32 bit integer 32 bit logical and 40 bit floating point data including single cycle integer and floating point conversions Results of the ALU are always maintained in 32 bit integer or 40 bit floating point formats The barrel shifter is used to shift up to 32 bits left or right in a single cycle See Chapter 5 Data Formats and Floating Point ...

Page 45: ...uch system functions as addressing stack management processor status interrupts and block repeat See Chapter 3 CPU Registers for more information Table 2 1 Primary CPU Registers Register Name Assigned Function Section Page R0 Extended precision register 0 3 1 1 3 3 R1 Extended precision register 1 3 1 1 3 3 R2 Extended precision register 2 3 1 1 3 3 R3 Extended precision register 3 3 1 1 3 3 R4 Ex...

Page 46: ...ations See Chapter 5 Data Formats and Floating Point Operation for extended precision register formats for floating point and integer numbers The 32 bit auxiliary registers AR7 AR0 are accessed by the CPU and modified by the two ARAUs The primary function of the auxiliary registers is the generation of 24 bit addresses They also can be used as loop counters or as 32 bit general purpose registers t...

Page 47: ...lows the status register to be easily saved and restored See Table 3 2 on page 3 6 for a list and definitions of the status regis ter bits The CPU DMA interrupt enable register IE is a 32 bit register The CPU interrupt enable bits are in locations 10 0 The DMA interrupt enable bits are in locations 26 16 A 1 in a CPU DMA interrupt enable register bit enables the corresponding interrupt A 0 disable...

Page 48: ...the PC is not part of the CPU register file it is a register that can be modified by instructions that modify the program flow The instruction register IR is a 32 bit register that holds the instruction opcode during the decode phase of the instruction This register is used by the instruction decode control circuitry and is not accessible to the CPU ...

Page 49: ...its and support two accesses in a single cycle A boot loader allows the loading of program and data at reset from 8 16 32 bit wide memories or serial port Figure 2 7 shows how the memory is organized on the C32 RAM blocks 0 and 1 are each 256 32 bits and support two accesses in a single cycle A boot loader allows the loading of program and data at reset from 1 2 4 8 16 and 32 bit wide memories or ...

Page 50: ... XD31 XD0 XA12 XA0 DMAADDR bus DMADATA bus DADDR2 bus DADDR1 bus DDATA bus PADDR bus PDATA bus Program counter instruction register CPU DMA controller 32 24 24 32 24 24 32 32 24 32 24 24 32 24 32 Peripheral bus Multiplexer Multiplexer Cache 64 32 RAM block 0 1K 32 RAM block 1 1K 32 ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ROM block 4K 32 ...

Page 51: ... W D31 D0 A23 A0 DMAADDR bus DMADATA bus DADDR2 bus DADDR1 bus DDATA bus PADDR bus PDATA bus Program counter instruction register CPU DMA controller 32 24 24 32 24 24 32 32 24 32 24 24 32 24 32 Peripheral bus Multiplexer Multiplexer Cache 64 32 RAM block 0 1K 32 RAM block 1 1K 32 ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ Boot ROM ...

Page 52: ...nterface STRB0_B2 A 2 STRB0_B1 STRB0_B0 STRB1_B3 A 1 STRB1_B2 A 2 STRB1_B1 STRB1_B0 IOSTRB Memory Organization 2 16 Figure 2 7 Memory Organization of the TMS320C32 A 64 32 bit instruction cache is provided to store often repeated sections of code which greatly reduces the number of off chip accesses This allows for code to be stored off chip in slower lower cost memories The external buses are als...

Page 53: ...J Register The operand is a CPU register J Short immediate The operand is a 16 bit short or 24 bit long imme diate value J Direct The operand is the contents of a 24 bit address formed by concatenating the 8 bits of data page pointer and a 16 bit operand J Indirect An auxiliary register indicates the address of the operand 3 operand instruction addressing modes J Register Same as for general addre...

Page 54: ... 32 bit program data bus PDATA These buses can fetch a single instruction word every machine cycle The 24 bit data address buses DADDR1 and DADDR2 and the 32 bit data data bus DDATA support two data memory accesses every machine cycle The DDATA bus carries data to the CPU over the CPU1 and CPU2 buses The CPU1 and CPU2 buses can carry two data memory operands to the multiplier ALU and register file...

Page 55: ...on by pro viding the flexibility to address 8 16 or 32 bit data independently of the exter nal memory width In this way the chip count and the size of external memory is reduced The number of memory chips can be further reduced by the C32 s ability to allow code execution from 16 or 32 bit wide memories The C32 memory interface also reduces the total amount of RAM by allowing the physical data mem...

Page 56: ... read ÁÁ ÁÁ ÁÁÁÁ ÁÁÁÁ Size ÁÁ ÁÁ 32 ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 4 cycle read ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 2 cycle read ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1 cycle read ÁÁ ÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁ ÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁ ÁÁ To access 8 16 or 32 bit data quantities types from 8 16 or 32 bit wide memory the memory interface uses either strobe STRB0 or STRB1 depending on the address location within the memory map Each strobe...

Page 57: ... The C30 and C31 external interrupts are level triggered To reduce external logic and simplify the interface the C32 external interrupts are edge and level or level only triggered The triggering is user selectable through a bit in the status register See Section 3 1 7 Status Register ST for more information Two external I O flags XF0 and XF1 can be configured as input or output pins under software...

Page 58: ... peripherals with their associated buses and signals See Chapter 12 Peripherals for more information Figure 2 9 Peripheral Modules ÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉ Serial port 0 Port control register R X timer register Data transmit register Data receive register Timer0 Global control register Timer period register Timer counter register Timer1 Global control r...

Page 59: ...eripherals for more information about timers 2 9 2 Serial Ports The bidirectional serial ports two on C30 one each on the C31 and C32 are totally independent They are identical to a complementary set of control registers that control each port Each serial port can be configured to transfer 8 16 24 or 32 bits of data per word The clock for each serial port can originate either internally or externa...

Page 60: ... C30 31 DMA with the addition of user configurable priorities Because the DMA and CPU have distinct buses on the C3x devices they can operate independently of each other However when the CPU and DMA access the same on chip or external resources the bandwidth can be exceeded and priorities must be established The C30 and C31 assign highest priority to the CPU The C32 DMA coprocessor provides more f...

Page 61: ...rchitectural Overview Figure 2 10 DMA Controller DMAADDR bus DMADATA bus DMA controller Global control register Source address register Destination address register Transfer counter register Peripheral address bus Peripheral data bus ...

Page 62: ...TMS320C30 TMS320C31 and TMS320C32 Differences 2 26 2 11 TMS320C30 TMS320C31 and TMS320C32 Differences Table 2 2 shows the major differences between the C32 C31 and the C30 devices ...

Page 63: ...32 bit wide memory IOSTRB active for 810000h 82FFFFh ROM 4k No No Boot loader No Yes Yes On chip RAM 2k address 809800h 809FFFh 2k address 809800h 809FFFh 512 address 87FE00h 87FFFFh DMA 1 channel CPU greater priority than DMA 1 channel CPU greater priority than DMA 2 channels Configurable priorities Serial ports 2 1 1 Timers 2 2 2 Interrupts Level triggered Level triggered Level triggered or com ...

Page 64: ...cision registers and index registers Three registers in the C32 CPU register file have been modified to support new features 2 channel DMAs program execution from 16 bit memory width etc The registers modified in the C32 are the status ST register interrupt enable IE register and interrupt flag IF register Topic Page 3 1 CPU Multiport Register File 3 2 3 2 Other Registers 3 18 3 3 Reserved Bits an...

Page 65: ... Extended precision register 4 3 1 1 3 3 R5 05 Extended precision register 5 3 1 1 3 3 R6 06 Extended precision register 6 3 1 1 3 3 R7 07 Extended precision register 7 3 1 1 3 3 AR0 08 Auxiliary register 0 3 1 2 3 4 AR1 09 Auxiliary register 1 3 1 2 3 4 AR2 0A Auxiliary register 2 3 1 2 3 4 AR3 0B Auxiliary register 3 3 1 2 3 4 AR4 0C Auxiliary register 4 3 1 2 3 4 AR5 0D Auxiliary register 5 3 1...

Page 66: ...onsist of two separate and distinct regions Bits 39 32 dedicated to storage of the exponent e of the floating point number Bits 31 0 store the mantissa of the floating point number J Bit 31 sign bit s J Bits 30 0 the fraction f Any instruction that assumes the operands are floating point numbers uses bits 39 0 Figure 3 1 illustrates the storage of 40 bit floating point numbers in the extended prec...

Page 67: ...ng on page 6 4 Data pages are 64K words long with a total of 256 pages Bits 31 8 are reserved you must always keep these set to 0 cleared 3 1 4 Index Registers IR0 IR1 The 32 bit index registers IR0 and IR1 are used by the ARAU for indexing the address See Chapter 6 Addressing Modes for more information 3 1 5 Block Size BK Register The 32 bit block size register BK is used by the ARAU in circular ...

Page 68: ...is allows the status register to be saved easily and restored At system reset a 0 is written to this register Figure 3 3 shows the format of the status register for the C30 and C31 devices Figure 3 4 shows the format of the status register for the C32 device Table 3 2 describes the status register bits their names and their functions Figure 3 3 Status Register TMS320C30 andTMS320C31 xx xx xx GIE C...

Page 69: ... overflow are treated in no special way If OVM 1 integer results overflowing in the positive direction are set to the most positive 2s complement number 7FFF FFFFh and integer results overflowing in the negative direction are set to the most negative 32 bit 2s complement number 8000 0000h RM 0 Repeat mode flag Repeat mode flag If RM 1 the PC is modified in either the repeat block or repeat single ...

Page 70: ...not frozen Cache enabled but frozen cache read only CC 0 Cache clear CC 1 invalidates all entries in the cache This bit is always cleared after it is written to and is always read as 0 At reset 0 is written to this bit GIE 0 Global interrupt enable If GIE 1 the CPU responds to an enabled interrupt If GIE 0 the CPU does not respond to an enabled interrupt INT config 0 Interrupt configuration C32 on...

Page 71: ...he PRGW status bit is set to 1 indicating a 16 bit memory width The C32 performs two fetches to retrieve a single 32 bit instruction word The PRGW bit is a read only bit and can have the following values PRG 0 1 Effect Instruction fetches use one 32 bit exter nal program memory read Instruction fetches use two 16 bit exter nal program memory reads Note If a load of the status register occurs simul...

Page 72: ...RINT1 DMA 23 R W EXINT1 DMA 22 R W ERINT0 DMA 21 R W EXINT0 DMA 20 R W EINT3 DMA 19 R W EINT2 DMA 18 R W EINT1 DMA 17 R W EINT0 DMA 16 R W xx 15 xx 14 xx 13 xx 12 xx EDINT CPU 10 R W ETINT1 CPU 9 R W ETINT0 CPU 8 R W ERINT1 CPU 7 R W EXINT1 CPU 6 R W ERINT0 CPU 5 R W EXINT0 CPU 4 R W EINT3 CPU 3 R W EINT2 CPU 2 R W EINT1 CPU 1 R W EINT0 CPU 0 R W 11 Notes 1 xx reserved bit read as 0 2 R read W wri...

Page 73: ...NT1 CPU 0 CPU DMA1 controller interrupt enable C32 only EINT0 DMA 0 DMA external interrupt 0 enable C30 and C31 only EINT1 DMA 0 DMA external interrupt 1 enable C30 and C31 only EINT2 DMA 0 DMA external interrupt 2 enable C30 and C31 only EINT3 DMA 0 DMA external interrupt 3 enable C30 and C31 only EINT0 DMA0 0 DMA0 external interrupt 0 enable C32 only EINT1 DMA0 0 DMA0 external interrupt 1 enable...

Page 74: ...DMA1 0 DMA1 external interrupt 0 enable C32 only EINT1 DMA1 0 DMA1 external interrupt 1 enable C32 only EINT2 DMA1 0 DMA1 external interrupt 2 enable C32 only EINT3 DMA1 0 DMA1 external interrupt 2 enable C32 only 3 1 9 CPU Interrupt Flag IF Register Figure 3 7 Figure 3 8 and Figure 3 9 show the 32 bit CPU interrupt flag reg isters IF for the C30 C31 and C32 devices respectively A 1 in a CPU IF re...

Page 75: ... Figure 3 8 TMS320C31 CPU Interrupt Flag IF Register yy yy xx 7 11 15 12 31 16 xx 10 DINT 9 TINT1 8 TINT0 5 RINT0 4 XINT0 3 INT3 2 INT2 1 INT1 xx 6 0 INT0 R W R W R W R W R W R W R W R W R W R W R W Notes 1 xx reserved bit read as 0 2 yy reserved bit set to 0 at reset 3 R read W write Figure 3 9 TMS320C32 CPU Interrupt Flag IF Register DINT1 xx xx 7 11 15 12 31 16 ITTP 10 DINT0 9 TINT1 8 TINT0 5 R...

Page 76: ...rt 1 receive interrupt flag C30 only TINT0 0 Timer 0 interrupt flag TINT1 0 Timer 1 interrupt flag DINT 0 DMA channel interrupt flag C30 and C31 only DINT0 0 DMA0 channel interrupt flag C32 only DINT1 0 DMA1 channel interrupt flag C32 only ITTP 0 Interrupt trap table pointer see Section 3 1 9 1 Allows the relocation of interrupt and trap vector tables C32 only Note If a load of the interrupt flag ...

Page 77: ...interrupt or trap vector is given by the addition of the effective base address formed by the ITTP bit field EA ITTP and the offset of the interrupt or trap vector in the interrupt trap vector table as shown in Figure 3 11 For example if the ITTP contains the value 100h the serial port transmit interrupt vector is located at 10005h Note that the vectors stored in the interrupt trap vector table ar...

Page 78: ... ITTP 20h TRAP0 EA ITTP 1Fh EA ITTP 0Dh DINT1 EA ITTP 0Ch DINT0 EA ITTP 0Bh TINT1 EA ITTP 0Ah TINT0 EA ITTP 09h EA ITTP 08h EA ITTP 07h RINT0 EA ITTP 06h XINT0 EA ITTP 05h INT3 EA ITTP 04h INT2 EA ITTP 03h INT1 EA ITTP 02h INT0 EA ITTP 01h EA ITTP 00h TRAP31 reserved TRAP30 reserved TRAP29 reserved TRAP28 reserved TRAP27 Reserved Reserved Reserved Reserved ...

Page 79: ...lag IOF Register R R W R W R R W R W INXF1 7 OUTXF1 6 I OXF1 5 INXF0 3 OUTXF0 2 I OXF0 1 xx 0 11 8 15 12 31 16 4 xx xx xx xx Notes 1 xx reserved bit read as 0 2 R read W write Table 3 5 IOF Bits and Functions Bit Name Reset Value Function I OXF0 0 If 0 XF0 is configured a general purpose input pin If 1 XF0 is configured a general purpose output pin OUTXF0 0 Data output on XF0 INXF0 0 Data input on...

Page 80: ...p is executed n 1 times The 32 bit repeat start address RS register contains the starting address of the program memory block to be repeated when the CPU is operating in the repeat mode The 32 bit repeat end address RE register contains the ending address of the program memory block to be repeated when the CPU is operating in the repeat mode Note RE RS If RE RS and the block mode is enabled the co...

Page 81: ... program counter register is not part of the CPU register file it can be modified by instructions that modify the program flow 3 2 2 Instruction Register IR The instruction register IR is a 32 bit register that holds the instruction op code during the decode phase of the instruction This register is used by the instruction decode control circuitry and is not accessible to the CPU ...

Page 82: ...y To retain compatibility with future members of the C3x family of microprocessors reserved bits that are read as 0 must be written as 0 You must not modify the current value of a reserved bit that has an undefined value In other cases you should maintain the reserved bits as specified ...

Page 83: ... on the C32 and a ROM block of 4K 32 bits available only on the C30 or boot loader available on the C31 and the C32 permit two CPU accesses in a single cycle A 64 32 bit instruction cache stores often repeated sections of code greatly reducing the number of off chip accesses and allowing code to be stored off chip in slower lower cost memories Topic Page 4 1 Memory 4 2 4 2 Reset Interrupt Trap Vec...

Page 84: ...ry Map The memory map depends on whether the processor is running in micro processor mode MC MP 0 or microcomputer mode MC MP 1 The memory maps for these modes are similar see Figure 4 1 on page 4 4 Locations 800000h 801FFFh are mapped to the expansion bus When this region is accessed MSTRB is active Locations 802000h 803FFFh are reserved Locations 804000h 805FFFh are mapped to the expansion bus W...

Page 85: ...rap vectors and a reserved space C30 Locations 1000h 7FFFFFh are accessed over the external memory port STRB active Section 4 1 2 Peripheral Bus Memory Map on page 4 9 describes the peripheral memory maps in greater detail and Section 4 2 Reset Interrupt Trap Vector Map on page 4 14 provides the vector locations for reset interrupts and traps Be careful Access to a reserved area produces unpredict...

Page 86: ...h RAM block 1 1K words internal 809C00h 809FFFh External STRB active 7 96M words 80A000h FFFFFFh Reset interrupt trap vectors and reserved locations 192 0h 0BFh 7FFFFFh Expansion bus MSTRB active 8K words 800000h 801FFFh Reserved 8K words 802000h 803FFFh Expansion bus IOSTRB active 8K words 804000h 805FFFh Reserved 8K words 806000h 807FFFh 808000h Peripheral bus memory mapped registers Internal 6K...

Page 87: ...nto the C3x memory map Locations 0h 03Fh consist of interrupt vector trap vector and reserved locations all of which are accessed over the external memory port STRB active see Figure 4 2 on page 4 6 Locations 040h 7FFFFFh are also accessed over the external memory port Microcomputer Mode In microcomputer mode the boot loader ROM is mapped into locations 0h 0FFFh The last 63 words 809FC1h to 809FFF...

Page 88: ...ve 7 96M words FFFFFFh 0h 0FFFh 1000h 7FFFFFh Reserved 32K words 800000h 807FFFh Peripheral bus memory mapped registers 6K words internal 808000h 8097FFh RAM block 0 1K words internal 809800h 809BFFh 809C00h 809FFFh 80A000h External STRB active 7 96M words FFFFFFh Boot 1 400000h RAM block 1 1K 63 words internal 809FC0h 809FC1h User program interrupt and trap branches 63 words internal Boot 3 FFF00...

Page 89: ... pro grammed through the interrupt trap table pointer ITTP bit field in the CPU inter rupt flag IF register See Section 3 1 9 1 Interrupt Trap Table Pointer ITTP on page 3 14 Microprocessor Mode In microprocessor mode the boot loader is not mapped into the C3x memory map Locations 0h 7FFFFFFh are accessed over the external memory port STRB0 active with location 0h containing the reset vector Micro...

Page 90: ...097FFh Reserved 319 5K words External memory IOSTRB active 128K 128K words External memory STRB0 active 512K words 82FFFFh 830000h 87FDFFh 87FE00h 87FEFFh 87FFFFh 880000h 900000h 8FFFFFh 87FF00h FFFFFFh 87FEFFh RAM block 1 256 words internal RAM block 0 256 words internal Reserved 319 5K words External memory IOSTRB active 128K 128K words Reserved 26K words 6K words internal memory mapped register...

Page 91: ...sections describe the peripherial bus memory maps for the C30 C31 and C32 4 1 2 1 TMS320C30 Peripheral Bus Memory Map The C30 memory mapped peripheral registers are located starting at address 808000h Figure 4 4 on page 4 10 shows the peripheral bus memory map The shaded blocks are reserved ...

Page 92: ... port 0 control Serial port 0 global control 808040h Timer 1 period register 808038h Timer 1 counter 808034h Timer 1 global control 808030h Timer 0 period 808028h Timer 0 counter 808024h Timer 0 global control 808020h DMA transfer counter 808008h DMA destination address 808006h DMA source address 808004h 808000h DMA global control Serial port 1 global control 808050h FSR DR CLKR serial port 1 cont...

Page 93: ...t data receive 808048h Serial port data transmit FSR DR CLKR serial port control 808046h Serial port R X timer period 808045h Serial port R X timer counter 808044h Serial port R X timer control 808043h 808042h FSX DX CLKX serial port control Serial port global control 808040h Timer 1 period register 808038h Timer 1 counter 808034h Timer 1 global control 808030h Timer 0 period 808028h Timer 0 count...

Page 94: ... 2 3 TMS320C32 Peripheral Bus Memory Map The C32 s memory mapped peripheral and external bus control registers are located starting at address 808000h as shown in Figure 4 6 on page 4 13 The shaded blocks are reserved ...

Page 95: ... X timer counter 808044h Serial port R X timer control 808043h 808042h FSX DX CLKX serial port control 808014h Serial port global control 808040h Timer 1 period register 808038h Timer 1 counter 808034h Timer 1 global control 808030h Timer 0 period 808028h Timer 0 counter 808024h Timer 0 global control 808020h DMA 1 transfer counter 808018h DMA 1 destination address 808016h DMA 1 source address 808...

Page 96: ...is loaded into the PC and execution begins from that address see Figure 4 8 on page 4 16 C31 Microcomputer Boot Loader Mode In the microcomputer boot loader mode of the C31 the interrupt and trap vectors stored in locations 809FC1h 809FFFh are branch instructions to the start of the respective interrupt and trap routines see Figure 4 9 on page 4 17 C32 Microprocessor and Microcomputer Boot Loader ...

Page 97: ...TMS320C30 Microprocessor Mode RESET 00h INT0 01h INT1 02h INT2 03h INT3 04h XINT0 05h RINT0 06h XINT1 07h RINT1 08h TINT0 09h TINT1 0Ah DINT 0Bh 0Ch 1Fh TRAP 0 20h D D D TRAP 27 3Bh 3Ch 3Dh 3Eh 3Fh Reserved TRAP 28 reserved TRAP 29 reserved TRAP 30 reserved TRAP 31 reserved Note Traps 28 31 Traps 28 31 are reserved do not use them ...

Page 98: ...r Mode 00h RESET 01h INT0 02h INT1 03h INT2 04h INT3 05h XINT0 06h RINT0 07h XINT1 Reserved 08h RINT1 Reserved 09h TINT0 0Ah TINT1 0Bh DINT 0Ch 1Fh Reserved 20h TRAP 0 3Bh TRAP 27 3Ch TRAP 28 reserved 3Dh TRAP 29 reserved 3Eh TRAP 30 reserved 3Fh TRAP 31 reserved Note Traps 28 31 Traps 28 31 are reserved do not use them ...

Page 99: ...INT0 809FCAh TINT1 809FCBh DINT 809FCCh 809FDFh Reserved 809FE0h TRAP 0 809FE1h TRAP 1 809FFBh TRAP 27 809FFCh TRAP 28 reserved 809FFDh TRAP 29 reserved 809FFEh TRAP 30 reserved 809FFFh TRAP 31 reserved Note Traps 28 31 Traps 28 31 are reserved do not use them Unlike the C31 s microprocessor mode the C31 microcomputer boot loader mode uses a dual vectoring scheme to service interrupts and trap req...

Page 100: ... EA ITTP 0Dh DINT1 EA ITTP 0Ch DINT0 EA ITTP 0Bh TINT1 EA ITTP 0Ah TINT0 EA ITTP 09h EA ITTP 08h EA ITTP 07h RINT0 EA ITTP 06h XINT0 EA ITTP 05h INT3 EA ITTP 04h INT2 EA ITTP 03h INT1 EA ITTP 02h INT0 EA ITTP 01h EA ITTP 00h TRAP31 reserved TRAP30 reserved TRAP29 reserved TRAP28 reserved TRAP27 Reserved Reserved Reserved Reserved Note Traps 28 31 Traps 28 31 are reserved do not use them ...

Page 101: ...is a corresponding single bit present P flag When the CPU requests an instruction word from external memory the cache algorithm checks to determine if the word is already contained in theinstruction cache Figure 4 11 shows how the cache control algorithm partitions an instruction address The algorithm uses the19 most significant bits MSBs of the instruction address to select the segment the five l...

Page 102: ...access to the cache Each time a segment is accessed its segment number is removed from the LRU stack and pushed onto the top of the LRU stack Therefore the number at the top of the stack is the most re cently used MRU segment number and the number at the bottom of thestack is the least recently used segment number At reset the LRU stack is initialized with 0 at the top and 1 at the bottom All P fl...

Page 103: ...r in parallel H The instruction word is read from memory and copied into the cache H The number of the segment containing the word is removed from the LRU stack and pushed to the top of the LRU stack if it is not already at the top thus moving the other segment number to the bottom of the stack H The relevant P flag is set J Segment miss Neither of the segment addresses matches the instruc tion ad...

Page 104: ...gn directive when coding assembly language 4 3 3 Cache Control Bits Three cache control bits are located in the CPU status register Cache Clear Bit CC Set CC 1 to invalidate all entries in the cache This bit is always cleared after it is written to it is always read as a 0 At reset the cache is cleared and 0 is written to this bit Cache Enable Bit CE Set CE 1 to enable the cache allowing the cache...

Page 105: ... or may not be fetched from the cache or external memory see Example 4 1 When the CC bit of the CPU status register is modified the following five instruc tions may or may not be fetched from the cache before the cache is cleared see Example 4 1 Example 4 1 Pipeline Effects of Modifying the Cache Control Bits Pipeline Operation Cycle Fetch Decode Read Execute n LDI 1000h ST n 1 LDI 1h R1 LDI 1000h...

Page 106: ...ating point operations at integer speeds while preventing problems with overflow operand alignment and other burdensome tasks that are common in integer operations This chapter discusses data formats and floating point operations supported in the C3x Topic Page 5 1 Integer Formats 5 2 5 2 Unsigned Integer Formats 5 3 5 3 Floating Point Formats 5 4 5 4 Floating Point Conversion IEEE Std 754 5 14 5 ...

Page 107: ...at is sign extended to 32 bits see Figure 5 1 The range of an integer si represented in the short integer format is 215 si 215 1 In Figure 5 1 s signed bit Figure 5 1 Short Integer Format and Sign Extension of Short Integers 15 0 15 16 31 0 Sign extension of a short integer s s s s s s s s s s s s s s s s s Short integer format s 5 1 2 Single Precision Integer Format In the single precision intege...

Page 108: ... unsigned integer operands For those instructions which assume unsigned integer operands this format is zero filled to 32 bits The range of a short unsigned integer is 0 si 216 Figure 5 3 Short Unsigned Integer Format and Zero Fill 15 0 15 16 31 0 Short unsigned integer format Zero fill of a short unsigned integer 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 2 2 Single Precision Unsigned Integer Format In th...

Page 109: ...igure 5 5 General Floating Point Format Exponent Sign Fraction Mantissa The general equation for calculating the value in a floating point number is x ss f2 2e In the equation s is the value of the sign bit s is the inverse of the value of the sign bit f is the binary value of the fraction field and e is the decimal equivalent of the exponent field The mantissa represents a normalized 2s complemen...

Page 110: ...ort Floating Point Format In the short floating point format floating point numbers are represented by a 2s complement 4 bit exponent field e and a 2s complement 12 bit mantissa field man with an implied most significant nonsign bit see Figure 5 6 Figure 5 6 Short Floating Point Format Exponent Sign Fraction 15 12 11 10 0 Mantissa Operations are performed with an implied binary point between bits ...

Page 111: ...format used in the C32 s instruction set In the short floating point format for external 16 bit data type size floating point numbers are represented by a 2s complement 8 bit exponent field e a sign bit s and an 8 bit mantissa field man with an implied most significant nonsign bit Figure 5 7 TMS320C32 Short Floating Point Format for External 16 Bit Data Exponent Sign Fraction 15 0 8 7 6 Mantissa O...

Page 112: ...ns store the value in the MSBs of the C32 s registers For example If AR1 4000h R1 00 00000000h the value stored at memory location 4000h is 0180h and STRB0 is configured for a physical memory size and data type size of 16 bits The result of ADDI AR1 R1 is R1 00 00000180h while The result of ADDF AR1 R1 is R1 01 C0000000h 3 0 since 4 0 1 0 3 0 5 3 3 Single Precision Floating Point Format In the sin...

Page 113: ...ion format the floating point number is represented by an 8 bit exponent field e and a 32 bit mantissa field man with an implied most significant nonsign bit see Figure 5 9 Figure 5 9 Extended Precision Floating Point Format Exponent Sign Fraction 39 32 31 30 0 Mantissa Operations are performed with an implied binary point between bits 31 and 30 When the implied most significant nonsign bit is mad...

Page 114: ...en convert the binary number to a decimal number If the MSB is 1 then comple ment the binary number add 1 to the result and then convert this binary number to a decimal number Step 2 Convert the mantissa field to its decimal representation The mantissa field is represented as a sign mantissa number with an implied 1 and an implied binary point between the sign bit and the frac tion field If the si...

Page 115: ...issa becomes 0111 0000000002 which is equivalent to 7 in decimal If on the other hand e 210 and man 01 100000000002 then the shifted mantissa becomes 0 01100000000002 which is equivalent to 3 8 in decimal The following examples illustrate how you can obtain the equivalent floating point value of a number in C3x floating point format Each of the examples uses the single precision floating point for...

Page 116: ... 0000 0000 0000 0000 0000 Binary value Exponent 0000 00012 1 Sign 1 Fraction 100002 Value 10 12 21 1012 3 Fraction Implied Sign Example 5 3 Fractional Number F B 4 0 0 0 0 0 Hex value 1111 1011 0100 0000 0000 0000 0000 0000 Binary value Exponent 1111 10112 5 Sign 0 Fraction 100002 Value 01 12 2 5 0000112 3 64 Fraction Implied Sign 2 5 2 6 ...

Page 117: ...ntation of 0 in that format In Figure 5 10 through Figure 5 13 s sign bit of the exponent y short mantissa and x short exponent Figure 5 10 Converting from Short Floating Point Format to Single Precision Floating Point Format Short floating point format Single precision floating point format y y 0 0 y x s s y y y x x s 15 12 11 10 0 31 27 24 23 22 12 11 0 x s s s x x In this format the exponent fi...

Page 118: ...recision floating point format 0 y x x y y y x x 31 24 23 22 0 39 32 30 31 0 y y 0 8 7 The 8 LSBs of the mantissa field are filled with 0s Figure 5 13 Converting from Extended Precision Floating Point Format to Single Precision Floating Point Format Extended precision floating point format z y x x 39 32 30 31 0 y y z 8 7 Single precision floating point format y y y x x 31 24 23 22 0 The 8 LSBs of ...

Page 119: ...a actually has 24 bits see Figure 5 14 There are several special cases summarized below These are the values of the represented numbers in the IEEE floating point format x 1 s x 2e 127 x 01 f if 0 e 255 Figure 5 14 IEEE Single Precision Std 754 Floating Point Format e f 31 23 22 0 s 30 mantissa The following five cases define the value v of a number expressed in the IEEE format 1 If e 255 and f 0 ...

Page 120: ...C3x Formats To differentiate between the symbols that define these two formats all IEEE fields are subscripted with an IEEE for example eIEEE sIEEE and so forth Similarly all 2s complement fields are subscripted with 2 that is e2 s2 f2 5 4 1 Converting IEEE Format to 2s Complement TMS320C3x Floating Point Format The most common conversion is the IEEE to 2s complement format This conversion is done...

Page 121: ...rmalized numbers with a nonzero fraction to the identical value in the 2s complement negative number Case 5 maps the IEEE negative normalized numbers with a 0 fraction to the identical value in the 2s complement negative number Case 6 maps the IEEE positive and negative denormalized numbers and positive and negative 0s to a 2s complement 0 Based on these definitions of the formats two versions of ...

Page 122: ...eith Henry of Apollo Computer Inc The other routines were based on this initial input Example 5 4 IEEE to TMS320C3x Conversion Fast Version TITLE IEEE TO TMS320C3x CONVERSION FAST VERSION SUBROUTINE FMIEEE FUNCTION CONVERSION BETWEEN THE IEEE FORMAT AND THE TMS320C3x FLOATING POINT FORMAT THE NUMBER TO BE CONVERTED IS IN THE LOWER 32 BITS OF R0 THE RESULT IS STORED IN THE UPPER 32 BITS OF R0 UPON ...

Page 123: ...nent PUSH R1 POPF R0 Load this as a flt pt number RETS NEG PUSH R1 POPF R0 Load this as a flt pt number NEGF R0 R0 Negate if orig sign is negative RETS Example 5 5 shows the complete conversion between IEEE and C3x formats In addition to the general case and the 0s it handles the special cases as follows If NaN e 255 f 0 the number is returned intact If infinity e 255 f 0 the output is saturated t...

Page 124: ...E ROUTINE AR1 POINTS TO THE FOLLOWING TABLE 0 0xFF800000 AR1 1 0xFF000000 2 0x7F000000 3 0x80000000 4 0x81000000 5 0x7F800000 6 0x00400000 7 0x007FFFFF 8 0x7F7FFFFF ARGUMENT ASSIGNMENTS ARGUMENT FUNCTION R0 NUMBER TO BE CONVERTED AR1 POINTER TO TABLE WITH CONSTANTS REGISTERS USED AS INPUT R0 AR1 REGISTERS MODIFIED R0 R1 REGISTER CONTAINING RESULT R0 NOTE SINCE THE STACK POINTER SP IS USED MAKE SUR...

Page 125: ...LDFZ AR1 3 R0 If not force the number to 0 RETSZ and return XOR AR1 6 R0 If MSB of f 1 make it 0 BND NEG1 LSH 1 R0 Eliminate sign bit line up mantissa SUBI AR1 2 R0 Make e 127 PUSH R0 POPF R0 Put number in floating point format RETS NEG1 POPF R0 NEGF R0 R0 If negative negate R0 RETS HANDLE THE REGULAR CASES NORMAL AND3 R0 AR1 R1 Replace fraction with 0 BND NEG Test sign ADDI R0 R1 Shift sign and e...

Page 126: ...0h f2 2s complement of f2 Case 1 maps a 2s complement 0 to a positive IEEE 0 Case 2 maps the 2s complement numbers that are too small to be repre sented as normalized IEEE numbers to a positive IEEE 0 Case 3 maps the positive 2s complement numbers that are not covered by case 2 into the identically valued IEEE number Case 4 maps the negative 2s complement numbers with a nonzero fraction that are n...

Page 127: ...x to IEEE conversion Example 5 6 TMS320C3x to IEEE Conversion Fast Version TITLE TMS320C3x TO IEEE CONVERSION FAST VERSION SUBROUTINE TOIEEE FUNCTION CONVERSION BETWEEN THE TMS320C3x FORMAT AND THE IEEE FLOATING POINT FORMAT THE NUMBER TO BE CONVERTED IS IN THE UPPER 32 BITS OF R0 THE RESULT WILL BE IN THE LOWER 32 BITS OF R0 UPON ENTERING THE ROUTINE AR1 POINTS TO THE FOLLOWING TABLE 0 0xFF800000...

Page 128: ...FZ AR1 4 R0 If 0 load appropriate number BND NEG Branch to NEG if negative delayed ABSF R0 Take the absolute value of the number LSH 1 R0 Eliminate the sign bit in R0 PUSHF R0 POP R0 Place number in lower 32 bits of R0 ADDI AR1 2 R0 Add exponent bias 127 LSH 1 R0 Add the positive sign RETS NEG POP R0 Place number in lower 32 bits of R0 ADDI AR1 2 R0 Add exponent bias 127 LSH 1 R0 Make space for th...

Page 129: ... BE IN THE LOWER 32 BITS OF R0 UPON ENTERING THE ROUTINE AR1 POINTS TO THE FOLLOWING TABLE 0 0xFF800000 AR1 1 0xFF000000 2 0x7F000000 3 0x80000000 4 0x81000000 5 0x7F800000 6 0x00400000 7 0x007FFFFF 8 0x7F7FFFFF ARGUMENT ASSIGNMENTS ARGUMENT FUNCTION R0 NUMBER TO BE CONVERTED AR1 POINTER TO TABLE WITH CONSTANTS REGISTERS USED AS INPUT R0 AR1 REGISTERS MODIFIED R0 REGISTER CONTAINING RESULT R0 NOTE...

Page 130: ... of the number LSH 1 R0 Eliminate the sign bit in R0 PUSHF R0 POP R0 Place number in lower 32 bits of R0 ADDI AR1 2 R0 Add exponent bias 127 LSH 1 R0 Add the positive sign CONT TSTB AR1 5 R0 RETSNZ If e 0 return TSTB AR1 7 R0 RETSZ If e 0 f 0 return PUSH R0 POPF R0 LSH 1 R0 Shift f right by one bit PUSHF R0 POP R0 ADDI AR1 6 R0 Add 1 to the MSB of f RETS NEG POP R0 Place number in lower 32 bits of...

Page 131: ...he extended precision format These multiplications occur in a single cycle Figure 5 16 is a flowchart that shows the steps involved in floating point multi plication Each step is labelled with a number in parenthesis In step 1 the 24 bit source operand mantissas are multiplied producing a 50 bit result c man Input and output data are always represented as normalized numbers In step 2 the exponents...

Page 132: ...the positive direction then step 14 sets c exp to the most positive extended precision format value If c exp has overflowed in the negative direction then step 14 sets c exp to the most negative extended precision format value If c exp has underflowed step 12 then step 15 sets c to 0 that is c man 0 and c exp 128 ...

Page 133: ...ormat Test for special cases of c man c man 1 and c exp c exp 1 c man 2 and c exp c exp 2 c exp 128 4 Right shift 1 to normalize 5 Right shift 2 to normalize 3 c man 0 6 No shift to normalize Dispose of extra bits Test for special cases of c exp 12 c exp underflow 13 c exp in range 11 c exp overflow If c man 0 set c exp to most positive value If c man 0 set c exp to most negative value c exp 128 c...

Page 134: ...ing to the normalized single precision floating point format Then 10 00000000000000000000000 2α exp 10 00000000000000000000000 2b exp 0100 000000000000000000000000000000000000000000000 2 α exp b exp To place this number in the proper normalized format it is necessary to shift the mantissa two places to the right and add 2 to the exponent This yields 10 00000000000000000000000 2α exp 10 00000000000...

Page 135: ... 2α exp 01 0000000000000000000000 2b exp 01 00100000000000000000000000000000000000000000000 2 α exp b exp 1 Example 5 10 Floating Point Multiply Both Mantissas 1 0 Let α 1 0 2α exp 01 00000000000000000000000 2α exp b 1 0 2b exp 01 00000000000000000000000 2b exp Where a and b are both represented in binary form according to the single preci sion floating point format Then 01 00000000000000000000000...

Page 136: ...0000000000000000000 x 2α exp b 2 0 x 2b exp 10 00000000000000000000000 x 2b exp Then 01 00000000000000000000000 2α exp x 10 00000000000000000000000 2b exp 1110 0000000000000000000000000000000000000000000000 2 α exp b exp The result is c 2 0 x 2 α exp b exp Example 5 12 Floating Point Multiply by 0 All multiplications by a floating point 0 yield a result of 0 f 0 s 0 and exp 128 ...

Page 137: ... In step 3 the mantissa with the smallest exponent in this case α man is right shifted d bits to align the mantissas In step 4 after the mantissas have been aligned they are added In steps 5 through 7 a check for a special case of c man If c man is 0 step 5 then c exp is set to its most negative value step 8 to yield the correct representation of 0 If c man has overflowed c step 6 then in step 9 c...

Page 138: ...extended precision floating point format Test for special cases of c man c exp 128 6 Overflow of c man 7 k of leading non significant sign bits 5 c man 0 Test for special cases of c exp 12 c exp underflow 13 c exp in range 11 c exp overflow If c man 0 set c to most positive value If c man 0 set c to most negative value set c to 0 c exp 128 c man 0 Set c to final result c α b 14 15 16 8 1 Compare e...

Page 139: ... 5 01 0000000000000000000000000000000 2 1 It is necessary to shift b to the right by 1 so that α and b have the same exponent This yields b 0 5 00 1000000000000000000000000000000 20 Then 01 10000000000000000000000000000000 2 00 10000000000000000000000000000000 20 010 00000000000000000000000000000000 20 As in the case of multiplication it is necessary to shift the binary point one place to the left...

Page 140: ...quired The exponent of the result is modified accordingly The result is 01 0000000000000000000000000000001 20 01 0000000000000000000000000000000 20 01 0000000000000000000000000000000 2 31 Example 5 15 Floating Point Addition With a 32 Bit Shift This example illustrates a situation where a full 32 bit shift is necessary to normalize the result Let α 01 1111111111111111111111111111111 2127 b 10 0000...

Page 141: ...traction 5 36 Example 5 16 Floating Point Addition Subtraction With Floating Point 0 When floating point addition and subtraction are performed with a floating point 0 the following identities are satisfied α 0 α α 0 0 0 0 0 α α α 0 ...

Page 142: ...be unnormalized the binary point is assumed to be man 0 0000000000000000001000000000001 exp 0 This number is then sign extended one bit so that the mantissa contains 33 bits man 00 0000000000000000001000000000001 exp 0 The intermediate result after the most significant nonsign bit is located and the shift performed is man 01 0000000000010000000000000000000 exp 19 The final 32 bit value output afte...

Page 143: ...c man c exp 128 1 α man 0 Test for special cases of c exp 6 c exp underflow 7 c exp in range c exp 128 No change to c man Set c to final result c norm α 8 9 3 Sign extended α man 1 bit c man α man k c exp α exp k 4 k of leading nonsignificant sign bits α Remove most significant nonsign bit 5 Leading nonsignificant sign bits 2 ...

Page 144: ...lowing opera tion is performed first c α man 2α exp 1 2α exp 24 Next a conversion from extended precision floating point to single precision floating point format is performed Given the extended precision floating point value the rounding rnd is performed as shown in Figure 5 19 Note RND src dst where src 0 does not set the 0 conditions flag bit 2 in the status register Instead it sets the underfl...

Page 145: ...128 c man 0 Test for special cases of c exp c exp overflow c exp in range Set eight LSBs of c man to 0 c rnd α c man c man 1 c exp α exp 1 α If c man 0 set c to most positive single precision value If c man 0 set c to most negative single precision value Overflow of c man Add α man and 1 2 of LSB c man α man 2 24 1 2 α exp 24 No special case ...

Page 146: ...n the range 231 α 231 1 First you must be certain that α exp 30 If these bounds are not met an overflow occurs If an overflow occurs in the positive direction the output is the most positive integer If an overflow occurs in the negative direction the output is the most negative integer If α exp is within the valid range then α man with implied bit included is sign extended and right shifted rs by ...

Page 147: ...20 Flowchart for Floating Point to Integer Conversion by FIX Instruction Test for special cases of α exp α exp 30 α exp in range rs 31 α exp Overflow Shift If α man 0 c most positive integer If α man 0 c most negative integer c α man rs Set c to final result α c fix α ...

Page 148: ...ision integers to be converted to extended precision floating point numbers The flowchart for this conversion is shown in Figure 5 21 Figure 5 21 Flowchart for Integer to Floating Point Conversion by FLOAT Instruction Test for special cases of c man c exp 128 c man 0 Leading nonsignificant sign bits Set c to final result c float α c man c man k c exp 30 k k leading nonsignificant sign bits α Remov...

Page 149: ...og form log2 X EXP_old log2 mant_old Log base two Since EXP is in the exponent register no calculation is needed and the value can be used directly as an integer To extract the value of the exponent PUSH POP and masking operations are used The remaining mantissa conversion is done by first forcing the exponent bits to zero using an LDE 1 0 instruction This causes the exponent term 2 EXP to equal 1...

Page 150: ...2 0 or 1 0 The TMS320C30 C40 extended register bit pattern for the algorithm sequence is shown below Table 5 3 Squaring Operation of F0 1 5 Squaring Operation of F0 1 5 Exp S Mantissa 00000000 0 1000000000000000000000000000000 X 1 5 Exp 0 00000001 0 0010000000000000000000000000000 X 2 2 25 Exp 1 00000010 0 0100010000000000000000000000000 X 4 5 0625 Exp 2 00000100 0 1001101000010000000000000000000 ...

Page 151: ...umbers exponent which rep resents the whole number part of the result becomes the eight MSBs of the final result Another technique is to look at the three MSBs of the mantissa and apply a roundup from the fourth bit Those same MSBs can be used as a quick exten sion of the exponent logarithm To visualize this consider the following tabu lated values and graph 1 0 0 585 0 5 0 0 1 0 1 5 2 0 Mantissa ...

Page 152: ...ced after the first three MPYF R0 R0 instructions remedy this but adds to the cycle count When the input value approaches 1 0 the result is driven close to zero and accuracy suffers In this case an input range comparison and a branch to a McLauren series expansion is used as a solution with minimal degradation in speed This is because the power series converges quickly for input values close to 1 ...

Page 153: ...E _log_E POP AR1 return address AR1 POPF R0 X R0 LDF R0 R1 use R1 to accumulate answer LDI 2 RC repeat 3x RPTB loop ASH 7 R1 LDE 1 0 R0 EXP 0 MPYF R0 R0 mant 2 MPYF R0 R0 mant 4 MPYF R0 R0 mant 8 MPYF R0 R0 mant 16 MPYF R0 R0 mant 32 MPYF R0 R0 mant 64 MPYF R0 R0 mant 128 PUSHF R1 PUSH EXP and Mantissa sign is now data POP R0 POP as ianteger EXP FRACTION BD AR1 FLOAT R0 convert EXP FRACTION to flo...

Page 154: ...addressing modes It also discusses the management of system stacks queues and dequeues in memory Topic Page 6 1 Addressing Types 6 2 6 2 Register Addressing 6 3 6 3 Direct Addressing 6 4 6 4 Indirect Addressing 6 5 6 5 Immediate Addressing 6 18 6 6 PC Relative Addressing 6 19 6 7 Circular Addressing 6 21 6 8 Bit Reversed Addressing 6 26 6 9 Aligning Buffers With the TMS320 Floating Point DSP Assem...

Page 155: ...ion Indirect addressing An auxiliary register contains the address of the operand Immediate addressing The operand is a 16 bit or 24 bit immediate value PC relative addressing A 16 bit or 24 bit displacement to the program counter PC Two specialized modes are available for use in filters FFTs and DSP algorithms Circular addressing An auxiliary register is incremented decremented with regards to a ...

Page 156: ... 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0FH 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh Extended precision register 0 Extended precision register 1 Extended precision register 2 Extended precision register 3 Extended precision register 4 Extended precision register 5 Extended precision register 6 Extended precision register 7 Auxiliary register 0 Auxiliary register 1 Auxiliary register 2 Auxiliar...

Page 157: ... and operation for direct addressing are Syntax expr Operation address DP concatenated with expr Figure 6 1 shows the formation of the data address Example 6 1 is an instruc tion example with data before and after instruction execution Figure 6 1 Direct Addressing 0 0 31 16 15 0 0 0 31 address operand page expr x x x x 0 0 31 8 7 0 24 23 31 DP Instruction word Data page pointer Example 6 1 Direct ...

Page 158: ...dify auxiliary registers in parallel with operations within the main CPU Indirect addressing is specified by a 5 bit field in the instruction word referred to as the mod field shown in Table 6 2 A displacement is either an explicit unsigned 8 bit integer contained in the instruction word or an implicit displace ment of 1 Two index registers IR0 and IR1 can also be used in indirect addressing enabl...

Page 159: ...oding LSB MSB 5 bits mod ARn disp 3 bits 0 5 or 8 bits Note Auxiliary Register The auxiliary register ARn is encoded in the instruction word according to its binary representation n for example AR3 is encoded as 112 not its register machine address shown in Table 6 1 ...

Page 160: ...postdisplacement subtract and circular modify b Indirect addressing with index register IR0 Mod Field Syntax Operation Description 01000 ARn IR0 addr ARn IR0 With preindex IR0 add 01001 ARn IR0 addr ARn IR0 With preindex IR0 subtract 01010 ARn IR0 addr ARn IR0 ARn ARn IR0 With preindex IR0 add and modify 01011 ARn IR0 addr ARn IR0 ARn ARn IR0 With preindex IR0 subtract and modify 01100 ARn IR0 add...

Page 161: ...nd modify 10110 ARn IR1 addr ARn ARn circ ARn IR1 With postindex IR1 add and circular modify 10111 ARn IR1 addr ARn ARn circ ARn IR1 With postindex IR1 subtract and circular modify d Indirect addressing special cases Mod Field Syntax Operation Description 11000 ARn addr ARn Indirect 11001 ARn IR0 B addr ARn ARn B ARn IR0 With postindex IR0 add and bit reversed modify Legend addr memory address cir...

Page 162: ...bler Syntax ARn disp Modification Field 00000 0 0 31 24 23 Address x ARn 31 disp 0 0 0 31 8 7 Integer Operand 0 0 x Example 6 4 Indirect Addressing With Predisplacement Subtract The address of the operand to fetch is the contents of an auxiliary register ARn minus the displacement disp The displacement is either an 8 bit unsigned integer contained in the instruction word or an implied value of 1 O...

Page 163: ...tax ARn disp Modification Field 00010 0 0 31 24 23 Address x x ARn 31 disp 0 0 0 31 8 7 Integer Operand 0 0 Example 6 6 Indirect Addressing With Predisplacement Subtract and Modify The address of the operand to fetch is the contents of an auxiliary register ARn minus the displacement disp The displacement is either an 8 bit unsigned integer contained in the instruction word or an implied value of ...

Page 164: ...bler Syntax ARn disp Modification Field 00100 Integer 0 0 31 24 23 Address x x 31 disp 0 0 0 31 8 7 Operand 0 0 ARn Example 6 8 Indirect Addressing With Postdisplacement Subtract and Modify The address of the operand to fetch is the contents of an auxiliary register ARn After the operand is fetched the displacement disp is subtracted from the auxiliary register The displacement is either an 8 bit ...

Page 165: ...ax ARn disp Modification Field 00110 0 0 31 24 23 Address x x ARn 31 disp 0 0 0 31 8 7 Integer Operand 0 0 Example 6 10 Indirect Addressing With Postdisplacement Subtract and Circular Modify The address of the operand to fetch is the contents of an auxiliary register ARn After the operand is fetched the displacement disp is subtracted from the contents of the auxiliary register using circular addr...

Page 166: ...n IRm Modification Field 01000 if m 0 10000 if m 1 0 0 31 24 23 Address x x ARn 31 IRm x 0 31 Index Operand x 24 23 Example 6 12 Indirect Addressing With Preindex Subtract The address of the operand to fetch is the difference of an auxiliary register ARn and an index register IR0 or IR1 Operation operand address ARn IRm Assembler Syntax ARn IRm Modification Field 01001 if m 0 10001 if m 1 0 0 31 2...

Page 167: ...m Modification Field 01010 if m 0 10010 if m 1 0 0 31 24 23 Address x x ARn 31 IRm x 0 31 Index Operand 24 23 x Example 6 14 Indirect Addressing With Preindex Subtract and Modify The address of the operand to fetch is the difference between an auxiliary register ARn and an index register IR0 or IR1 The resulting address becomes the new contents of the auxiliary register Operation operand address A...

Page 168: ...n IRm Modification Field 01100 if m 0 10100 if m 1 Index 0 0 31 24 23 Address x x ARn 31 x x 0 31 24 23 Operand IRm Example 6 16 Indirect Addressing With Postindex Subtract and Modify The address of the operand to fetch is the contents of an auxiliary register ARn After the operand is fetched the index register IR0 or IR1 is subtracted from the auxiliary register Operation operand address ARn ARn ...

Page 169: ...ification Field 01110 if m 0 10110 if m 1 Index 0 0 31 24 23 Address x x ARn 31 x x 0 31 24 23 Operand IRm Example 6 18 Indirect Addressing With Postindex Subtract and Circular Modify The address of the operand to fetch is the contents of an auxiliary register ARn After the operand is fetched the index register IR0 or IR1 is subtracted from the auxiliary register This result is evaluated using cir...

Page 170: ... operand is fetched the index register IR0 is added to the auxiliary register This addition is performed with a reverse carry propagation and can be used to yield a bit reversed B address This value replaces the contents of the auxiliary register Operation operand address ARn ARn B ARn IR0 Assembler Syntax ARn IR0 B Modification Field 11001 0 0 31 24 23 Address x x ARn 31 x x 0 31 24 23 Index Oper...

Page 171: ...xample 6 20 illustrates an instruction example with data before and after the instruction is executed Example 6 20 Short Immediate Addressing SUBI 1 R0 Before Instruction After Instruction R0 00 0000 0000 R0 00 FFFF FFFF In long immediate addressing the operand is a 24 bit unsigned immediate value contained in the 24 LSBs of the instruction word expr This is the syntax for this mode Syntax expr Ex...

Page 172: ... the PC during the pipeline decode phase Notice that because the PC is incremented by 1 in the fetch phase the displacement is added to this incremented PC value Syntax expr src Example 6 22 illustrates an example with data from before and after the instruction is executed Example 6 22 PC Relative Addressing BU NEWPC pc 1001h NEWPC label 1005h displacement 3 Before Instruction After Instruction de...

Page 173: ...C Relative Addressing Mode a BR BRD unconditional branches standard and delayed 31 25 24 23 0 0 1 1 0 0 0 0 0 Displacement b CALL unconditional subroutine call 31 24 23 0 0 1 1 0 0 0 1 0 Displacement c RPTB repeat block 31 25 24 23 0 0 1 1 0 0 1 0 0 Displacement ...

Page 174: ...f the buffer the device sets the pointer to the beginning of the buffer For example Figure 6 4a shows a circular buffer that holds six values Figure 6 4b shows how this buffer is implemented in the C3x memory space Figure 6 5 shows this buffer after writing three values Figure 6 6 shows this buffer after writing eight values Figure 6 4 Logical and Physical Representation of Circular Buffer Start E...

Page 175: ...are identical Specify the size of the circular buffer R by storing the length of the buffer in the block size register BK The size of the buffer must be less than or equal to 64K 16 bits Align the start of the buffer to a K bit boundary that is the K LSBs of the starting address of the circular buffer must be 0 by satisfying the following formula 2K R where R length of circular buffer K number of ...

Page 176: ...tep BK index index step Else if index step BK index index step BK Else if index step 0 index index step BK Figure 6 7 shows how the circular buffer is implemented and illustrates the relationship of the quantities generated and the elements in the circular buffer Figure 6 7 Circular Buffer Implementation Top of circular buffer H H 0 0 H H H H L L LSBs BK Element 0 Element 1 Element K LSBs of ARn L...

Page 177: ... 2nd 5th 4th 3rd 1st Value Data Address Circular addressing is especially useful for the implementation of FIR filters Figure 6 8 shows one possible data structure for FIR filters Note that the ini tial value of AR0 points to h N 1 and the initial value of AR1 points to x 0 Circular addressing is used in the C3x code for the FIR filter shown in Example 6 25 Figure 6 8 Data Structure for FIR Filter...

Page 178: ...alization LDP HADDR LDI N BK Load block size LDI HADDR AR0 Load pointer to impulse re sponse LDI XADDR AR1 Load pointer to bottom of input sample buffer TOP LDF IN R3 Read input sample STF R3 AR1 Store with other samples and point to top of buffer LDF 0 R0 Initialize R0 LDF 0 R2 Initialize R2 Filter RPTS N 1 Repeat next instruction MPYF3 AR0 AR1 R0 ADDF3 R0 R2 R2 Multiply and accumulate ADDF R0 R2...

Page 179: ...r K number of 0s in the LSBs of the buffer table starting address Size of the buffer table must be less than or equal to 64K 16 bits The CPU bit reversed operation can be illustrated by assuming an FFT table of size 2n When real and imaginary data are stored in separate arrays the n LSBs of the base address must be 0 and IR0 must be equal to 2n 1 half of the FFT size When real and imaginary data a...

Page 180: ...lue AR2 AR2 0110 1110 7th value Table 6 3 shows the relationship of the index steps and the four LSBs of AR2 You can find the four LSBs by reversing the bit pattern of the steps Table 6 3 Index Steps and Bit Reversed Addressing Step Bit Pattern Bit Reversed Pattern Bit Reversed Step 0 0000 0000 0 1 0001 1000 8 2 0010 0100 4 3 0011 1100 12 4 0100 0010 2 5 0101 1010 10 6 0110 0110 6 7 0111 1110 14 8...

Page 181: ...ct assembly directives to define a section in conjunction with the align memory allocation parameter of the sections directive of the linker command file For the FIR filter of Example 6 25 with a length of 32 the linker command file is MEMORY RAM origin 0h length 1000h SECTIONS text RAM Impulse_Resp ALIGN 64 RAM Input_Buf ALIGN 64 RAM Aligning Buffers With the TMS320 Floating Point DSP Assembly La...

Page 182: ...s a double ended queue linear list for which insertions and deletions are made at either end of the list 6 10 1 System Stack Pointer The system stack pointer SP is a 32 bit register that contains the address of the top of the system stack The system stack fills from low memory address to high memory address see Figure 6 9 The SP always points to the last element pushed onto the stack A push perfor...

Page 183: ... two cases The only difference is that in case 1 the AR always points to the top of the stack and in case 2 the AR alwayspoints to the next free location on the stack Figure 6 10 Implementations of High to Low Memory Stacks Top of stack Low memory High memory Free Bottom of stack ARn Top of stack Low memory High memory Free Bottom of stack Case 1 Case 2 ARn Stack growth from low to high memory can...

Page 184: ... The implementation of queues is based on the manipu lation of auxiliary registers Two auxiliary registers are used one to mark the front of the queue from which data is popped or dequeued and the other to mark the rear of the queue where data is pushed With proper management of the auxiliary registers the queue can also be circular A queue is circular when the rear pointer is allowed to point to ...

Page 185: ...returns Hardware control includes reset operation interrupts and power management You can select the constructs best suited for your particular application Topic Page 7 1 Repeat Modes 7 2 7 2 Delayed Branches 7 9 7 3 Calls Traps and Returns 7 11 7 4 Interlocked Operations 7 13 7 5 Reset Operation 7 21 7 6 Interrupts 7 26 7 7 DMA Interrupts 7 38 7 8 Traps 7 47 7 9 Power Management Modes 7 49 Chapte...

Page 186: ...tial execution of the loop All subsequent executions of the loop have no overhead 0 cycle Three registers RS RE and RC control the updating of the program counter PC when it is modified in a repeat mode Table 7 1 describes these registers Table 7 1 Repeat Mode Registers Register Function RS ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Repeat start address register Holds the address ...

Page 187: ...register repeat end address register with the PC after the execution of each instruction If they match and the repeat counter RC is nonnegative the RC is decremented the PC is loaded with the repeat start address and the processing continues The fetches and appropriate status bits are modified as necessary Note that the RC is never modified when the RM flag is 0 The repeat counter should be loaded...

Page 188: ...of the block RC 1 RC Decrement RC if RC 0 If RC is not negative RS PC Set PC to start of block else if RC 0 If RC is negative 0 ST RM Turn off repeat mode bits 0 S Clear S PC 1 PC Increment PC 7 1 3 RPTB Instruction The RPTB instruction repeats a block of code a specified number of times The number of times to repeat the block is the RC repeat count register value plus 1 Because the execution of R...

Page 189: ...0 Note You can stop the loop from repeating before its completion by writing a 0 to the repeat counter or writing a 0 to the RM bit of the status register 7 1 4 RPTS Instruction An RPTS src instruction repeats the instruction following the RPTS src 1 times Repeats of a single instruction initiated by RPTS are not interruptible because the RPTS fetches the instruction word only once and then keeps ...

Page 190: ... the program counter no other instruction can modify the program counter at the same time Two rules apply Rule 1 The last instruction in the block or the only instruction in a block of size 1 cannot be a Bcond BR DBcond CALL CALLcond TRAP cond RETIcond RETScond IDLE RPTB or RPTS Example 7 3 shows an incorrectly placed standard branch Rule 2 None of the last four instructions from the bottom of the...

Page 191: ...he instruc tion being executed the RC register decrements to 0000 0000h Example 7 5 illustrates a pipeline conflict See Chapter 8 for pipeline information RPTS normally decrements the RC register to FFFF FFFFh However if the RPTS has a pipeline conflict on the last cycle the RC register decrements to 0000 0000h Note Number of Repetitions In any case the number of repetitions is always RC 1 Example...

Page 192: ...st be restored last after the RC RE and RS registers ST must be restored after restoring RC because the RM bit cannot be set to 1 if the RC register is 0 or 1 For this reason if you execute a POP ST instruction with ST RM bit 1 while RC 0 the POP instruction recovers all the ST register bits but not the RM bit that stays at 0 repeat mode disabled Also RS and RE must be correctly set before you act...

Page 193: ... D BRD and DBcond D Conditional delayed branches use the conditions that exist at the end of the instruction immediately preceding the delayed branch They do not depend on the instructions following the delayed branch The condition flags are set by a previous instruction only when the destination register is one of the extended precision registers R0 R7 or when one of the compare instructions CMPF...

Page 194: ...r speed This is shown in Example 7 7 where a NOP takes the place of the third unused instruction after the delayed branch Example 7 7 Delayed Branch Execution TITLE DELAYED BRANCH EXECUTION LDF AR1 5 R2 Load contents of memory to R2 BGED SKIP If loaded number 0 branch delayed LDFN R2 R1 If loaded number 0 load it to R1 SUBF 3 0 R1 Subtract 3 from R1 NOP Dummy operation to complete delayed branch M...

Page 195: ... 12 on page 13 30 J The src is either a PC relative displacement or is in register addres sing mode The condition flags are set by a previous instruction only when the destination register is one of the extended precision registers R0 R7 or when one of the compare instructions CMPF CMPF3 CMPI CMPI3 TSTB or TSTB3 is executed The TRAPcond instruction also executes only if a specific condition is tru...

Page 196: ...errupts are automatically disabled when a trap is executed This allows critical code to execute without risk of being interrupted Traps are generally terminated with a RETIcond instruction to reenable interrupts You can use traps to indirectly call functions This is particularly benefi cial when a kernel of code contains the basic subfunctions to be used by applications In this case you can modify...

Page 197: ...g point value into a register interlocked Signal interlocked src dst LDII Load integer into a register interlocked Signal interlocked src dst SIGI Signal interlocked Signal interlocked Clear interlock STFI Store floating point value to memory interlocked Clear interlock src dst STII Store integer to memory interlocked Clear interlock src dst The interlocked operations use the two external flag pin...

Page 198: ...xcept for the special use of XF0 and XF1 The src operand for LDFI and LDII is always a direct or indirect memory address XF0 is set to 0 only if the src is located off chip that is STRB STRB0 STRB1 MSTRB or IOSTRB is active or the src is one of the on chip peripherals If on chip memory is accessed then XF0 is not asserted and the operation executes as an LDF or LDI from internal memory The STFI an...

Page 199: ...alue might be loaded into the register Interrupting an LDFI LDII or SIGI instruction allows you to implement protection mechanisms against deadlock conditions by interrupting an interlocked load that has taken too long Upon return from the interrupt the next instruction is executed The STFI and STII instructions are not interruptible Since the STFI and STII instructions complete when ready is sign...

Page 200: ... count of the number of times a particular operation must be performed This operation may be per formed by any processor in the system If the count is 0 the processor waits until it is nonzero before beginning processing The example also shows the algorithm for modifying COUNT correctly Example 7 9 Multiprocessor Counter Manipulation CT OR 4 IOF XF0 1 Interlocked operation ended LDII COUNT R1 Inte...

Page 201: ...ed Semaphores are variables that can take only nonnegative integer values Two primitive indivisible operations are defined on semaphores with S being a semaphore V S S 1 S P S P if S 0 go to P else S 1 S Indivisibility of V S and P S means that when these processes access and modify the semaphore S they are the only processes doing so To enter a critical section a P operation is performed on a com...

Page 202: ...flicts when executing out of cache on chip memory or zero wait state memory LDII S R0 Interlocked read of S begins Contents of S R0 BZ P If S 0 go to P and try again SUBI 1 R0 Decrement R0 S STII R0 S Update S end interlock XF0 1 The SIGI operation can synchronize at an instruction level multiple C3xs Consider two processors connected as shown in Figure 7 3 The code for the two processors is shown...

Page 203: ... occurs 7 4 3 Pipeline Effects of Interlocked Instructions Before performing an interlocked instruction the XF0 pin must be configured as an output pin and the XF1 pin must be configured as an input pin through the IOF register see subsection 3 1 10 I O Flag Register IOF on page 3 16 After the XF0 and XF1 pins are configured no interlocked instruction can occur in the following two instructions ...

Page 204: ...R1 NOP NOP n 5 LDII AR1 R1 NOP n 6 LDII AR1 R1 STFI and STII instructions drive the XF0 pin high during its execution phase LDFI LDII and SIGI instructions sample the XF1 pin during its decode phase while driving the XF0 pin low during its read phase Therefore do not use an LDFI LDII or SIGI instruction immediately after an STFI or STII instruction see Example 7 14 Example 7 14 Incorrect Use of In...

Page 205: ...cording to whether the pin is reset synchronously or asynchronously Table 7 3 TMS320C3x Pin Operation at Reset Device Signal Operation at Reset C30 C31 C32 Primary Bus Interface Signals D31 D0 Synchronous reset placed in high impedance state n n n A23 A0 Synchronous reset placed in high impedance state n n n R W Synchronous reset deasserted by going to a high level n n n IOSTRB Synchronous reset d...

Page 206: ...a high level n n n MC MP or MCBL MP Reset has no effect n n n SHZ Reset has no effect n n n XF1 XF0 Asynchronous reset placed in high impedance state n n n Serial Port 0 Signals CLKX0 Asynchronous reset placed in high impedance state n n n DX0 Asynchronous reset placed in high impedance state n n n FSX0 Asynchronous reset placed in high impedance state n n n CLKR0 Asynchronous reset placed in high...

Page 207: ... Oscillator Signals VDD Reset has no effect n n n IODVDD Reset has no effect n ADVDD Reset has no effect n PDVDD Reset has no effect n DDVDD Reset has no effect n MDVDD Reset has no effect n VSS Reset has no effect n n n DVSS Reset has no effect n n CVSS Reset has no effect n n IVSS Reset has no effect n n VBBP Reset has no effect n n VSUBS Reset has no effect n n n X1 Reset has no effect n n X2 C...

Page 208: ...and Reserved EMU0 Undefined n n n EMU1 Undefined n n n EMU2 Undefined n n n EMU3 Undefined n n n EMU4 Undefined n EMU5 Undefined n EMU6 Undefined n RSV0 Undefined n RSV1 Undefined n RSV2 Undefined n RSV3 Undefined n RSV4 Undefined n RSV5 Undefined n RSV6 Undefined n RSV7 Undefined n RSV8 Undefined n RSV9 Undefined n RSV10 Undefined n ...

Page 209: ...with the status of the PRGW pin J IE CPU DMA interrupt enable flags J IF CPU interrupt flags J IOF I O flags The reset vector is read from memory location 0h On the C32 this is a 32 bit data read Once read this value is loaded into the PC This vector contains the start address of the system reset routine At this point code location is dictated by the PC Multiple C3x devices driven by the same syst...

Page 210: ...l interrupts can be found in Sec tion 12 3 7 DMA and Interrupts on page 12 64 Section 12 1 8 Timer Inter rupts on page 12 13 and Section 12 2 11 Serial Port Interrupt Sources on page 12 34 7 6 1 TMS320C30 and TMS320C31 Interrupt Vector Table Table 7 4 and Table 7 5 contain the interrupt vectors In the microprocessor mode of the C30 and the C31 Table 7 4 and the microcomputer mode of the C31 Table ...

Page 211: ...ty 06h RINT0 Internal interrupt generated when serial port 0 transmit buffer is full 07h XINT1 Internal interrupt generated when serial port 1 transmit buffer is empty 08h RINT1 Internal interrupt generated when serial port 1 transmit buffer is full 09h TINT0 Internal interrupt generated by timer0 0Ah TINT1 Internal interrupt generated by timer1 0Bh DINT Internal interrupt generated by DMA control...

Page 212: ...n the INT3 pin 809FC6 RINT0 Internal interrupt generated when serial port 0 transmit buffer is empty 809FC7 XINT1 Reserved 809FC8 RINT1 Reserved 809FC9 TINT0 Internal interrupt generated by timer0 809FCA TINT1 Internal interrupt generated by timer1 809FCB DINT Internal interrupt generated by DMA controller 809FCC 809FDF Reserved 809FE0 TRAP0 Internal interrupt generated by TRAP 0 instruction 809FE...

Page 213: ...s EA ITTP as shown in Figure 7 4 Therefore the location of an interrupt or trap vector is given by the addition of the effective base address formed by the ITTP bit field EA ITTP and the offset of the interrupt or trap vector in the interrupt trap vector table as shown in Table 7 6 For example if the ITTP contains the value 100h the serial port transmit interrupt vector will be located at 10005h N...

Page 214: ...l interrupt generated when serial port 0 transmit buffer is full EA ITTP 07h Reserved EA ITTP 08h Reserved EA ITTP 09h TINT0 Internal interrupt generated by timer0 EA ITTP 0Ah TINT1 Internal interrupt generated by timer1 EA ITTP 0Bh DINT0 Internal interrupt generated by DMA channel 0 EA ITTP 0Ch DINT1 Internal interrupt generated by DMA channel 1 EA ITTP 0Dh Reserved EA ITTP 1Fh Reserved EA ITTP 2...

Page 215: ...Interrupt Vector Location Priority Function RESET 0h 0 External reset signal input on the RESET pin INT0 1h 1 External interrupt on the INT0 pin INT1 2h 2 External interrupt on the INT1 pin INT2 3h 3 External interrupt on the INT2 pin INT3 4h 4 External interrupt on the INT3 pin XINT0 5h 5 Internal interrupt generated when serial port 0 transmit buffer is empty RINT0 6h 6 Internal interrupt genera...

Page 216: ...evel triggered interrupts if INTn is still low when the interrupt acknowledge signal occurs the interrupt flag bit is cleared for only one cycle and then set again because INTn is still low Depending on when the IF register is read it is also possible that this bit may be 0 even though INTn is 0 When the C3x is reset 0 is written to the interrupt flag register clearing all pending interrupts The i...

Page 217: ...rupt processing flow for the exact sequence see Table 7 8 on page 7 36 For a CPU interrupt to occur at least two conditions must be met All interrupts must be enabled globally by setting the GIE bit to 0 in the status register The interrupt must be enabled by setting the corresponding bit in the IF register In the CPU interrupt processing cycle left side of Figure 7 6 the corresponding interrupt f...

Page 218: ...s PC interrupt vector PC SP Clear interrupt flag Disable interrupts GIE 0 If enabled interrupt is a CPU interrupt Is an enabled interrupt set No Yes Note CPU and DMA Interrupts CPU interrupts are acknowledged responded to by the CPU on instruction fetch boundaries only If instruction fetches are halted because of pipeline conflicts or execution of RPTS loops CPU interrupts are not acknowledged unt...

Page 219: ...upts are held until after the branch When an interrupt occurs instructions currently in the decode and read phases continue regular execution unlike an instruction in the fetch phase J If the interrupt occurs in the first cycle of the fetch of an instruction the fetched instruction is discarded not executed and the address of that instruction is pushed to the top of the system stack J If the inter...

Page 220: ... isr1 8 Execute first instruction of interrupt service routine isr4 isr3 isr2 isr1 7 6 8 External Interrupts The four external maskable interrupt pins INT0 INT3 are enabled at the IF reg ister Section 3 1 9 CPU Interrupt Flag IF Register on page 3 11 and are syn chronized internally They are sampled on the falling edge of H1 and passed through a series of H1 H3 latches internally These latches req...

Page 221: ...gram control until the ST GIE bit is set back to 1 On a return from an interrupt routine the RETI and RETIcond instructions set the ST GIE bit to 1 On the C30 and C31 external interrupts are level triggered On the C32 external interrupts are edge or level triggered depending on the INT config bit field of the status register For an edge triggered interrupt to be detected by the C32 the external pi...

Page 222: ...set value 002 in START bits DMA reset clears the interrupt internal latch 7 7 1 DMA Interrupt Control Bits Two registers contain bits used to control DMA interrupt operation CPU DMA interrupt enable register IE All DMA interrupts are controlled by the most significant 16 bits in the IE register and by the SYNC bits of the DMA channel control registers see Section 12 3 3 DMA Registers on page 12 51...

Page 223: ...the DMA coprocessor Figure 7 8 DMA Interrupt Processing DMA proceeds according to DMA control register SYNC bits Is an enabled interrupt set If enabled in the IE register the interrupt Is a DMA interrupt Clear interrupt flag DMA continues No Yes For more information about DMA interrupts see Section 12 3 7 DMA Interrupts on page 12 64 ...

Page 224: ...s may be accomplished by using an interrupt that causes the CPU to trap to an interrupt routine that contains an IDLE instruction Then if the same interrupt is used to synchronize DMA transfers the DMA transfer counter can be used to generate an interrupt and thus return control to the CPU following the DMA transfer Since the DMA and CPU share the same set of interrupt flags the DMA may clear an i...

Page 225: ...e interrupt recognition attempts to read or modify the status register For example if the status register is being pushed onto the stack it will be stored incorrectly if an interrupt was acknowledged two cycles before the store instruction When an interrupt signal is recognized the C3x continues executing the instructions already in the read and decode phases in the pipeline However because the in...

Page 226: ... 7 10 Pipeline Operation with Load Followed by Interrupt Cycle Description Fetch Decode Read Execute 1 LDI 2 Interrupt recognized LDI 3 Interrupt resets GIE bit clears interrupt flag reads SP interrupt LDI 4 GIE set by load instruction interrupt vector table read and ST saved on stack interrupt LDI 5 Store return address on stack interrupt 6 Fetch first instruction of ISR with GIE 1 ISR A similar ...

Page 227: ...reads or POP IE writes to ST register Added instruction to avoid pipeline problems In summary the next three instructions immediately following an instruction that clears the GIE bit might be interrupted Also the next three instructions immediately following an instruction that sets the GIE bit might not be interrupted even if there is a pending interrupt see Example 7 15 Similarly the next three ...

Page 228: ...porarily disabled to ensure that the trap executes before a subsequent interrupt If a pipeline conflict occurs and causes a delay in execution of the conditional trap the interrupt disabled condition may become the last known condition of the GIE bit If the trap condition is false interrupts are permanently disabled until the GIE bit is intentionally set The condition is not present when the trap ...

Page 229: ...erated internally for example a direct memory access DMA interrupt This situation arises as a result of a deci sion to poll certain interrupts or a desire to clear pending interrupts due to a long pulse width In the case of a long pulse width the interrupt may be generated after the CPU responds to the interrupt and attempts to auto matically clear it by the interrupt vector process The recommende...

Page 230: ..._START STI DP DUMMY_INT Set DUMMY_INT 0 POP R0 POP DP POP ST Housekeeping return from interrupt RETI ISR_n_START Normal interrupt service routine Code goes here LDI INT_Fn R0 AND IF R0 If ones in IF reg match BNZ ISR_n_END INT_Fn exit ISR LDI 0 DP Otherwise clear LDI 0FFFFh R0 DP and set STI R0 DUMMY_INT DUMMY_INT negative exit ISR_n_END POP R0 POP DP Exit ISR POP ST RETI ...

Page 231: ...ways triggered by a software mechanism by the TRAPcond conditional trap instructions Interrupts are always triggered by hardware events for example by exter nal interrupts DMA interrupts or serial port interrupts The GIE bit in the ST register and the mask bits in the IE do not apply to traps 7 8 2 Operation of Traps Figure 7 10 shows the general flow of traps which is similar to interrupts Figure...

Page 232: ... 32 different traps When a TRAPcond n instruction is executed the C3x jumps to the address stored in the memory location pointed to by the corresponding trap vector table pointer The location of the trap vector table is shown in Table 7 4 on page 7 27 C30 C31 microprocessor mode Table 7 5 C31 microcomputer boot mode on page 7 28 and Table 7 6 on page 7 30 for the C32 ...

Page 233: ... the bus until IDLE2 is exited This can be advantageous for low power applications since the bus is frozen in an active state That is the device pins are not floating and therefore do not require pullup or pulldowns When the device is in the functional nonemulation mode the clocks stop with H1 high and H3 low see Figure 7 11 The devices remain in IDLE2 until one of the four external interrupts INT...

Page 234: ...ruction is executed When the device is in emulation mode the H1 and H3 clocks continue to run normally and the CPU operates as if an IDLE instruction was executed The clocks continue to run for correct operation of the emulator Delayed Branch For correct device operation the three instructions following a delayed branch should not include either IDLE or IDLE2 instructions Figure 7 11 IDLE2 Timing ...

Page 235: ...POWER In the LOPOWER low power mode the CPU continues to execute instructions and the DMA can continue to perform transfers but at a reduced clock rate of CLKIN frequency divided by 16 A C31 with a CLKIN frequency of 32 MHz performs identically to a 2 MHz C31 with an instruction cycle time of 1 000 ns During the read phase of the The C31 and C32 LOPOWER instruction Figure 7 13 Slow to 1 16 of full...

Page 236: ...Power Management Modes 7 52 Figure 7 13 LOPOWER Timing 32 CLKIN H1 H3 CLKIN LOPOWER read Figure 7 14 MAXSPEED Timing H1 H3 CLKIN MAXSPEED read 32 CLKIN ...

Page 237: ...pelining is the overlapping or parallel operations of the fetch decode read and execute levels of a basic instruction The DMA controller decreases pipeline interference and enhances the CPU s computational throughput by performing input output operations Topic Page 8 1 Pipeline Structure 8 2 8 2 Pipeline Conflicts 8 4 8 3 Resolving Register Conflicts 8 19 8 4 Memory Access for Maximum Performance ...

Page 238: ...equired results of previous operations are written to memory All instruction executions perform these four basic functions fetch decode read and execute Figure 8 1 illustrates these four levels of the pipeline structure The levels are indexed according to instruction and execution cycle In the figure per fect overlap in the pipeline where all four units operate in parallel occurs at cycle m Levels...

Page 239: ...wn data and address buses In the C32 the DMA has configurable priorities Therefore priorities from highest to lowest have been assigned to each of the functioned units of the pipeline and to the DMA controller as follows DMA if configured with highest priority Execute Read Decode Fetch DMA if configured with lowest priority A pipeline conflict occurs when an instruction is being processed and is r...

Page 240: ...Y indi cates that a unit is ready If the particular unit does not perform a function the nop label is placed in that stage of the pipeline 8 2 1 Branch Conflicts The first class of pipeline conflicts occurs with standard nondelayed branches that is BR Bcond DBcond CALL IDLE RPTB RPTS RETIcond RETScond interrupts and reset Conflicts arise with these instructions and operations because during their ...

Page 241: ...flushing of the pipeline occurs Thus RS RE and RC can be used as general purpose 32 bit registers without pipeline conflicts When RPTB is nested because of nested interrupts it may be necessary to load and store these registers directly while using the repeat modes Since up to four instructions can be fetched before entering the repeat mode you should follow loads by a branch to flush the pipeline...

Page 242: ... the pertinent register is not ready to be used Some conditions under which you can avoid register conflicts are discussed in Sec tion 8 3 on page 8 19 The registers comprise the following three functional groups Group 1 This group includes auxiliary registers AR0 AR7 index registers IR0 IR1 and block size register BK Group 2 This group includes the data page pointer DP Group 3 This group includes...

Page 243: ...r DB instruction Example 8 3 Write to an AR Followed by an AR for Address Generation LDI 7 AR2 7 AR2 NEXT MPYF AR2 R0 Decode delayed 2 cycles ADDF FLOAT Pipeline Operation PC Fetch Decode Read Execute n LDI n 1 MPYF LDI n 2 ADDF MPYF LDI n 2 ADDF MPYF nop LDI 7 AR2 n 2 ADDF MPYF nop nop n 3 FLOAT ADDF MPYF nop The case for reads of these groups is similar to the cases for writes If an instruction ...

Page 244: ...DDF MPYF ADDI n 2 ADDF MYPF nop ADDI AR0 AR1 R0 n 3 FLOAT ADDF MPYF nop Note Loop counter auxiliary registers for the decrement and branch DBR instruc tions are regarded in the same way as they are for addressing The operation shown in Example 8 3 and Example 8 4 also can occur for this instruction 8 2 3 Memory Conflicts Memory conflicts can occur when the memory bandwidth of a physical memory spa...

Page 245: ...e program fetch from beginning The start of a CPU data access when J Two CPU data accesses are made to an internal RAM or ROM block and a program fetch from the same block is necessary J One of the external ports is starting a CPU data access and a program fetch from the same port is necessary A multicycle CPU data access or DMA data access over the external bus is needed Example 8 5 illustrates a...

Page 246: ... DMA requires The DMA begins a multicycle access The program fetch corresponding to the CALL is made to the same external port that the DMA is using Either of two cases may produce this situation One of the following two memory boundaries is crossed J From internal memory to external memory J From one external port to another Code that has been cached is executed and the instruction prior to the A...

Page 247: ... MPYF ADDF n 3 wait SUBF MPYF ADDF n 3 CALL nop SUBF MPYF n 4 CALL nop SUBF 8 2 3 2 Program Fetch Incomplete A program fetch incomplete occurs when an instruction fetch takes more than one cycle to complete because of wait states In Example 8 7 the MPYF and ADDF are fetched from memory that supports single cycle accesses The SUBF is fetched from memory requiring one wait state One example that dem...

Page 248: ...sses in a single cycle There are two cases in which this occurs An instruction performs a store and is followed by an instruction that performs two memory reads An instruction performs two stores and is followed by an instruction that performs at least one memory read An interlocked load LDII or LDFI instruction is performed and XF1 1 The first case is shown in Example 8 8 Since this sequence requ...

Page 249: ...ration Example 8 8 Single Store Followed by Two Reads STFR 0 AR1 R0 AR1 LDF AR2 R1 AR2 R1 in parallel with LDF AR3 R2 AR3 R2 Pipeline Operation PC Fetch Decode Read Execute n STF n 1 LDF LDF STF n 2 W LDF LDF STF n 3 X W LDF LDF STF n 4 X W LDF LDF nop n 4 Y X W LDF LDF Note W X Y Instruction representations ...

Page 250: ...wed by Single Read STF R0 AR0 R0 AR0 in parallel with STF R2 AR1 R2 AR1 ADDF SUM R1 R1 SUM R1 IACK ASH Pipeline Operation PC Fetch Decode Read Execute n STF STF n 1 ADDF STF STF n 2 IACK ADDF STF STF n 3 ASH IACK ADDF STF STF n 4 ASH IACK ADDF nop n 4 ASH IACK ADDF The final case involves an interlocked load LDII or LDFI instruction and XF1 1 Since the interlocked loads use the XF1 pin as an ackno...

Page 251: ...ad or store cannot be performed because an external port is busy An external load takes more than one cycle Conditional calls and traps which take one more cycle than conditional branches are processed The first type of hold everything conflict occurs when one of the external ports is busy because an access has started but is not complete In Example 8 11 the first store is a 2 cycle store The CPU ...

Page 252: ...e n STF n 1 LDF STF n 2 W LDF STF n 2 W LDF nop STF n 2 W LDF nop nop n 3 X W LDF nop n 4 Y X W LDF Note W X Y Instruction representations The second type of hold everything conflict involves multicycle data reads The read has begun and continues until completed In Example 8 12 the LDF is performed from an external memory that requires several cycles to access ...

Page 253: ...truction representations The final type of hold everything conflict deals with conditional calls CALLcond and traps TRAPcond which are different from other branch instructions Whereas other branch instructions are conditional loads the conditional calls and traps are conditional stores which take one more cycle to complete than conditional branches see Example 8 13 The added cycle pushes the retur...

Page 254: ...mple 8 13 Conditional Calls and Traps Pipeline Operation PC Fetch Decode Read Execute n CALLcond n 1 I CALLcond n 1 nop nop CALLcond n 1 nop nop nop CALLcond n 1 nop nop nop CALLcond n 2 CALLaddr I nop nop nop Note I Instruction representation ...

Page 255: ... delays are presented in Section 8 2 on page 8 4 Example 8 14 Example 8 15 and Example 8 16 demonstrate some common uses of these registers that do not produce a conflict or ways that you can avoid the conflict Example 8 14 Address Generation Update of an AR Followed by an AR for Address Generation LDF 7 0 R0 7 0 R0 MPYF AR0 IR1 R0 ADDF AR2 R0 FIX MPYF ADDF Pipeline Operation PC Fetch Decode Read ...

Page 256: ... Followed by an AR for Address Generation Without a Pipeline Conflict LDI TABLE AR2 MPYF VALUE R1 ADDF R2 R1 MPYF AR2 R1 SUBF STF Pipeline Operation PC Fetch Decode Read Execute n LDI n 1 MYPF LDI n 2 ADDF MYPF LDI n 3 MYPF ADDF MYPF LDI n 4 SUBF MYPF ADDF MYPF n 5 STF SUBF MYPF ADDF ...

Page 257: ...ite to DP Followed by a Direct Memory Read Without a Pipeline Conflict LDP TABLE_ADDR POP R0 LDF AR3 2 R1 LDI TABLE_ADDR AR0 PUSHF R6 PUSH R4 Pipeline Operation PC Fetch Decode Read Execute n LDP n 1 POP LDP n 2 LDF POP LDP n 3 LDI LDF POP LDP n 4 PUSHF LDI LDF POP n 5 PUSH PUSHF LDI LDF ...

Page 258: ...hen it is necessary to do a program fetch and a single data access and still achieve maximum performance one cycle Four cases achieve 1 cycle maximization Table 8 1 One Program Fetch and One Data Access for Maximum Performance Case No Primary Bus Accesses Accesses From Dual Access Internal Memory Expansion Bus or Peripheral Accesses 1 1 1 2 1 1 3 2 from any combination of internal memory 4 1 1 The...

Page 259: ... Peripheral Bus Accesses 1 1 2 from any combination of internal memory 2 1 program 1 data 1 data 3 1 data 1 data 1 program 4 1 data 1 program 1 data 1 DMA 5 2 from same internal memory block and 1 from a different internal memory block 6 3 from different internal memory blocks 7 2 from any combination of internal memory 1 8 1 program 2 data 1 DMA 9 1 DMA 2 data 1 program The expansion bus is avail...

Page 260: ...eads and writes can be defined according to these minor clock periods The types of memory operations that can occur are program fetches data loads and stores and DMA accesses 8 5 1 Program Fetches Internal program fetches are always performed during H3 unless a single data store must occur at the same time due to another instruction in the pipeline In that case the program fetch occurs during H1 a...

Page 261: ...they complete with the latching of the data word at the end of H1 In the case of a data store bits 15 0 represent the dst operand Internal data stores are performed during H3 External data stores always start at the beginning of H3 with the address and data being presented on the external bus Figure 8 3 2 Operand Instruction Word 31 0 X 0 Operation dst src G src dst 24 23 16 15 8 7 0 8 5 2 2 3 Ope...

Page 262: ...cond cycle Ordering the operands so that src1 is located internally is necessary to achieve single cycle execution If src1 and src2 are both from external memory two cycles are required to complete the two reads In the first cycle the src1 access is performed and loaded on the next H3 in the second cycle the src2 access is performed and loaded on that cycle s H1 If src2 is in external memory and s...

Page 263: ...DDI3 AR1 AR3 R0 AR3 points to on chip RAM src1 AR1 points to MSTRB space src2 H1 H3 Pipeline Operation PC Fetch Decode Read Execute n STI n 1 ADDI3 STI n 2 ADDI3 STI n 3 STI n 4 n 5 ADDI3 n 6 n 7 ADDI3 n 8 ADDI3 Two cycles are required for the MSTRB store Two additional cycles are required for the dummy MSTRB read of AR3 because a read follows a write One cycle is required for an actual MSTRB read...

Page 264: ...ing Alternative Switch the operands of the 3 operand instruction so that the internal read is performed first STI R0 AR6 AR6 points to MSTRB space ADDI3 AR3 AR1 R0 AR3 points to on chip RAM src2 AR1 points to MSTRB space src1 H1 H3 Pipeline Operation PC Fetch Decode Read Execute n STI n 1 ADDI3 STI n 2 ADDI3 STI n 3 STI n 4 n 5 ADDI3 n 6 n 7 ADDI3 n 8 ADDI3 ...

Page 265: ...6 15 8 7 0 P d2 src2 src3 The instruction word format for instructions that have parallel stores to memory is shown in Figure 8 6 If both destination operands dst1 and dst2 are located in internal memory dst1 is stored during H3 and dst2 during H1 thus completing two memory stores in a single cycle Figure 8 6 Two Parallel Stores 31 1 1 src2 dst2 24 23 16 15 8 7 0 src1 dst1 ST ST 0 0 0 If dst1 is i...

Page 266: ... src4 24 23 16 15 8 7 0 src1 src3 Operation d1 d2 src2 For these operations src3 and src4 are both located in memory If both operands are located in internal memory src3 is performed during H3 and src4 is per formed during H1 thus completing two memory reads in a single cycle If src3 is in internal memory and src4 is in external memory the src4 access begins at the start of H3 and latches at the e...

Page 267: ...ansion bus On the C31 one bus the primary bus is available to access external memories and peripheral devices You can control wait state generation permitting access to slower memories and peripherals by manipulating memory mapped control registers associated with the interfaces and by using an external input signal Topic Page 9 1 Overview 9 2 9 2 Memory Interface Signals 9 3 9 3 Memory Interface ...

Page 268: ... 13 bit address bus and a set of control signals Each interface has the following features Separate configurations controlled by memory mapped external interface control registers Hold request and acknowledge signal for putting the external memory inter face signals in high impedance mode and preventing the processor from accessing the external bus Selectable wait state that can be controlled thro...

Page 269: ... active strobe signal STRB MSTRB or IOSTRB When a primary bus access is performed STRB is low The expansion bus of the C30 supports two types of accesses Memory access signaled by MSTRB low The timing for an MSTRB access is the same as that of the STRB access on the primary bus External peripheral device access is signaled by IOSTRB low Each of the buses primary and expansion has an associated con...

Page 270: ...A O Z Hold acknowledge for external memory interface 1 1 RDY I Indicates external primary interface is ready to be accessed NA Ignored A 23 0 O Z Primary address bus When the primary bus address lines are not in high impedance state due to HOLD signal they keep in the last exter nal primary bus access HI Address of last external bus access D 31 0 I O Z Primary data bus These signals go to high imp...

Page 271: ...emory active high or write active low mode 1 1 XRDY I Indicates external expansion interface is ready to be accessed NA Ignored XA 12 0 O Expansion address bus When the expansion bus address lines are not in high impedance state due to HOLD signal they keep the last external expansion bus access HI Address of last external expansion bus access XD 31 0 I O Z Expansion data bus These signals go to h...

Page 272: ...us control C30 only 808060h 808061h 808062h 808063h 808064h 808065h 808066h 808067h 808068h 808069h 80806Ah 80806Bh 80806Ch 80806Dh 80806Fh Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Primary bus control C30 C31 Peripheral Address Reserved ...

Page 273: ...hat contains the control bits for the primary bus see Figure 9 2 Table 9 3 describes the register bits with the bit names and functions Figure 9 2 Primary Bus Control Register 2 1 0 SWW WTCNT BNKCMP xx xx 3 4 5 6 7 8 9 10 11 12 15 13 31 16 HOLDST NOHOLD HIZ R W R W R W R R W R W Notes 1 xx reserved bit read as 0 2 R read W write Note After changing the bit fields of the primary bus control registe...

Page 274: ...is asserted if an internal hold is generated HIZ 1 HIZ 0 Internal hold When set HIZ 1 the port is put in hold mode This is equivalent to the external HOLD signal By forcing a high impedance condition the C3x can relinquish the exter nal memory port through software HOLDA goes low when the port is placed in the high impedance state SWW 11 Software wait mode In conjunction with WTCNT this 2 bit fiel...

Page 275: ...s Control Register Bits Abbreviation Reset Value Name Description SWW 11 Software wait mode In conjunction with the WTCNT 2 bit field defines the mode of wait state generation See Table 9 5 WTCNT 111 Software wait mode This 3 bit field specifies the number of cycles to use when in software wait mode for the generation of internal wait state The range is 0 WTCNT 0 0 0 to 7 WTCNT 1 H1 H3 cycles See ...

Page 276: ...generate the internal ready signal RDYint that controls accesses As long as RDYint 1 the current external access is delayed When RDYint 0 the current access completes Since the use of programmable wait states for both external interfaces is identical only the primary bus interface is described in the following paragraphs RDYwtcnt is an internally generated ready signal When an external access is b...

Page 277: ...al Description 00 0 1 x x 0 1 Wait until external RDY is signaled 01 x x 0 1 0 1 Wait until internal wait state generator counts down to 0 10 0 0 1 1 0 1 0 1 0 0 0 1 Wait until first signal external RDY or the internal wait state generator logical OR 11 0 0 1 1 0 1 0 1 0 1 1 1 Wait until both external RDY is signaled and wait state generator counts down to 0 logical AND ...

Page 278: ...t LSBs yielding a bank size of 256 words If BNKCMP 16 only the 16 MSBs are compared Bank sizes from 28 256 to 224 16M are allowed Table 9 6 summarizes the relation ship between BNKCMP the address bits used to define a bank and the resulting bank size Figure 9 4 BNKCMP Example 23 8 7 0 24 bit address Number of bits to compare Defines bank size Table 9 6 BNKCMP and Bank Size BNKCMP MSBs Defining a B...

Page 279: ...TRB is inactive high The contents of the internal register are replaced with the MSBs being used for the current read of the current address If the MSBs of the address being used for the current read match the bits in the register a normal read cycle takes place If repeated reads are performed from the same memory bank no extra cycles are inserted When a read is performed from a different memory b...

Page 280: ...le Bank Switching 9 14 Figure 9 5 Bank Switching Example H3 H1 STRB R W A D RDY Read Read Read Extra cycle Note After changing BNKCMP up to three instructions are fetched before the change in the bank size occurs ...

Page 281: ... R W X A X D and X RDY are used to symbolize the equivalent primary and expan sion bus signals The IOSTRB expansion bus cycles are timed differently and are discussed independently 9 6 1 Primary Bus Cycles All bus cycles comprise integral numbers of H1 clock cycles One H1 cycle is defined to be from one falling edge of H1 to the next falling edge of H1 For full speed zero wait state accesses write...

Page 282: ...rising if the previous H1 cycle was the active portion of a write If the previous H1 cycle was a read address changes on the next H1 falling Figure 9 6 illustrates a read read write sequence for M STRB active and no wait states The data is read as late in the cycle as possible to allow maximum access time from address valid Although external writes require two cycles internally from the perspectiv...

Page 283: ...y Interface Figure 9 6 Read Read Write for M STRB 0 H3 H1 M STRB X R W X A X D X RDY Read Read Write data Note x RDY is sampled low on rising edge of H1 Data is read next falling edge of H1 Note Back to Back Read Operations M STRB remains low during back to back read operations ...

Page 284: ...s a write write read sequence for M STRB active and no wait states The address and data written are held valid approximately one half cycle after M STRB changes Figure 9 7 Write Write Read for M STRB 0 H3 H1 X A X D X R W M STRB X RDY Write data Write data Read ...

Page 285: ...ure 9 8 illustrates a read cycle with one wait state Since X RDY 1 the read cycle is extended M STRB X R W and X A are also extended one cycle The next time X RDY is sampled it is 0 Figure 9 8 Use of Wait States for Read for M STRB 0 H3 H1 X A X D XR W M STRB X RDY Write data Extra cycle Read ...

Page 286: ... with one wait state Since initially X RDY 1 the write cycle is extended M STRB X R W and X A are extended one cycle The next time X RDY is sampled it is 0 Figure 9 9 Use of Wait States for Write for M STRB 0 H3 H1 X A X D X RDY M STRB X R W Write data Write data Extra cycle ...

Page 287: ...d H1 cycle The IOSTRB signal always goes inactive high between cycles and XR W is high for reads and low for writes Figure 9 10 illustrates read and write cycles when IOSTRB is active and there are no wait states For IOSTRB accesses reads and writes require a minimum of two cycles Some off chip peripherals might change their status bits when read or written to Therefore it is important to maintain...

Page 288: ...illustrates a write with one wait state when IOSTRB is active For each wait state added IOSTRB XR W and XA are extended one clock cycle Writes hold the data on the bus one additional cycle The sampling of XRDY is repeated each cycle Figure 9 11 Read With One Wait State for IOSTRB 0 H3 H1 XA XD XR W IOSTRB XRDY Read Extra cycle ...

Page 289: ...External Memory Interface Timing 9 23 TMS320C30 and TMS320C31 External Memory Interface Figure 9 12 Write With One Wait State for IOSTRB 0 H3 H1 XA XD XR W IOSTRB XRDY Write data Extra cycle ...

Page 290: ...ough Figure 9 23 illustrate the various transitions between memory reads and writes and I O writes over the expansion bus Figure 9 13 Memory Read and I O Write for Expansion Bus H3 H1 XA XD XR W IOSTRB MSTRB XRDY Memory address I O address Read I O write ...

Page 291: ... Memory Interface Timing 9 25 TMS320C30 and TMS320C31 External Memory Interface Figure 9 14 Memory Read and I O Read for Expansion Bus XRDY XD XA XR W IOSTRB MSTRB H1 H3 I O read Read I O address Memory address ...

Page 292: ...External Memory Interface Timing 9 26 Figure 9 15 Memory Write and I O Write for Expansion Bus H3 H1 XA XD XRDY MSTRB IOSTRB XR W Memory address I O address I O write Memory write ...

Page 293: ...ry Interface Timing 9 27 TMS320C30 and TMS320C31 External Memory Interface Figure 9 16 Memory Write and I O Read for Expansion Bus H3 H1 XA XD XRDY MSTRB IOSTRB XR W Memory address I O address I O read Memory write ...

Page 294: ...External Memory Interface Timing 9 28 Figure 9 17 I O Write and Memory Write for Expansion Bus H3 H1 XA XD XRDY MSTRB IOSTRB XR W I O address Memory address I O write Memory write ...

Page 295: ...Memory Interface Timing 9 29 TMS320C30 and TMS320C31 External Memory Interface Figure 9 18 I O Write and Memory Read for Expansion Bus H3 H1 XA XD XRDY MSTRB IOSTRB XR W I O address Memory address I O write Read ...

Page 296: ...External Memory Interface Timing 9 30 Figure 9 19 I O Read and Memory Write for Expansion Bus I O address Memory address Memory write XRDY XD XA XR W IOSTRB MSTRB H1 H3 I O read ...

Page 297: ... Memory Interface Timing 9 31 TMS320C30 and TMS320C31 External Memory Interface Figure 9 20 I O Read and Memory Read for Expansion Bus Memory address I O address XRDY XD XA XR W IOSTRB MSTRB H1 H3 Read I O read ...

Page 298: ...External Memory Interface Timing 9 32 Figure 9 21 I O Write and I O Read for Expansion Bus I O write XRDY XD XA XR W IOSTRB MSTRB H1 H3 I O read I O address I O address ...

Page 299: ...Memory Interface Timing 9 33 TMS320C30 and TMS320C31 External Memory Interface Figure 9 22 I O Write and I O Write for Expansion Bus I O write I O write XRDY XD XA XR W IOSTRB MSTRB H1 H3 I O address I O address ...

Page 300: ...External Memory Interface Timing 9 34 Figure 9 23 I O Read and I O Read for Expansion Bus I O read I O read XRDY XD XA XR W IOSTRB MSTRB H1 H3 I O address I O address ...

Page 301: ...al states when a bus is inactive after an IOSTRB or M STRB access respectively The strobes STRB MSTRB and IOSTRB and X R W go to 1 The address is driven with last exter nal bus access and the ready signal XRDY or RDY is ignored Figure 9 24 Inactive Bus States for IOSTRB H3 H1 XA XD XR W IOSTRB XRDY Write data XRDY ignored Bus inactive ...

Page 302: ...External Memory Interface Timing 9 36 Figure 9 25 Inactive Bus States for STRB and MSTRB H3 H1 X A X D X R W M STRB X RDY Write data X RDY ignored Bus inactive ...

Page 303: ...chronous input There is a minimum of one cycle delay from the time when the processor recognizes HOLD 0 until HOLDA 0 When HOLDA 0 the address data buses and associated strobes are placed in a high impedance state All accesses occurring over an interface are completed before a hold is acknowledged Figure 9 26 HOLD and HOLDA Timing H3 H1 HOLD HOLDA STRB R W A D Write data Bus inactive ...

Page 304: ...nd enhancements in detail Topic Page 10 1 TMS320C32 Memory Features 10 2 10 2 TMS320C32 Memory Overview 10 3 10 3 Configuration 10 7 10 4 Programmable Wait States 10 15 10 5 Programmable Bank Switching 10 17 10 6 32 Bit Wide Memory Interface 10 20 10 7 16 Bit Wide Memory Interface 10 26 10 8 8 Bit Wide Memory Interface 10 32 10 9 External Ready Timing Improvement 10 38 10 10 Bus Timing 10 39 Chapt...

Page 305: ...s STRB0 and STRB1 and one IOSTRB allow zero glue logic interface to two banks of memory and one bank of external peripherals Separate bus control registers for each strobe control wait state genera tion external memory width and data type size Each memory STRB handles 8 16 or 32 bit external data accesses reads and writes to 8 16 or 32 bit wide memory Multiprocessor support through the HOLD and HO...

Page 306: ...TRBxB1 and STRBx_B0 These signals serve as byte enable pins to access one byte half word or a full word from the external memory The first two signals also serve as additional address pins to perform two or four consecutive accesses in 8 bit or 16 bit wide external memory The C32 controls the behavior of these pins through the data size and memory width bit fields in the corresponding strobe contr...

Page 307: ...npacks the data accessed accordingly Figure 10 1 Memory Address Spaces C32 Strobe control registers 32 bit CPU PRGW pin STRB0 STRB1 IOSTRB Memory interface 8 16 32 bit data in 8 16 32 bit wide memory Program in 16 32 bit wide memory 8 16 32 bit data in 8 16 32 bit wide memory 32 bit data in 32 bit wide memory Program in 16 32 bit wide memory Program in 32 bit wide memory 10 2 2 Program Memory Acce...

Page 308: ... reset The physical memory width is set to 16 bit memory width if the PRGW pin is logic high after the device reset see Section 10 3 for more information The cycle before and the cycle after changing the PRGW should not perform a program fetch over the external memory interface 10 2 3 Data Memory Access The C32 can load and store 8 16 or 32 bit data quantities from and into memory Because the CPU ...

Page 309: ... C32 Short Floating Point Format for External 16 Bit Data on page 5 6 When a 16 bit floating point value is loaded into a 40 bit register the external memory interface zero fills the least signifi cant 24 bits of the register When a 16 bit floating point value is used as a 32 bit on chip input operand the external memory interface zero fills the 16 LSBs of the 32 bit input operand The 32 bit float...

Page 310: ...an assign these values to the C32 memory interface through bit fields in the bus control registers 10 3 1 External Interface Control Registers The following sections describe the bus control registers used to manipulate the byte addressability features of the C32 Figure 10 3 shows the external interface control memory map Figure 10 3 Memory Mapped External Interface Control Registers ÁÁÁÁ ÁÁÁÁ Add...

Page 311: ...ÁÁ ÁÁÁÁÁÁÁÁ WTCNT ÁÁÁÁÁ ÁÁÁÁÁ SWW ÁÁÁ ÁÁÁ HIZ ÁÁÁÁ ÁÁÁÁ NOHOLD ÁÁÁÁ ÁÁÁÁ HOLDST Á Á Á Á ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ R W ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ R W ÁÁÁÁÁ ÁÁÁÁÁ R W ÁÁÁ ÁÁÁ R W ÁÁÁÁ ÁÁÁÁ R W ÁÁÁÁ ÁÁÁÁ R Á Á Notes 1 R read W write 2 xx reserved read as 0 10 3 1 2 STRB1 Control Register The STRB1 control register Figure 10 5 is a 32 bit register that contains the control bits for the portion of the externa...

Page 312: ...TRB Unlike the STRB0 and STRB1 there is no byte enable signal for the IOSTRB The data access through the IOSTRB is always 32 bit The following table lists the register bits with the bit names and functions At the system reset 0F8h is written to the IOSTRB control register The IOSTRB timing is identical to the C30 IOSTRB timing Figure 10 6 IOSTRB Control Register ÁÁ ÁÁ ÁÁÁÁÁ ÁÁÁÁÁ 31 16 ÁÁÁÁÁÁ ÁÁÁÁ...

Page 313: ... register only HIZ 0 Internal hold When set HIZ 1 the port is put in hold mode This is equivalent to the external HOLD signal By forcing the high impedance condition the C3x can relinquish the external memory port through software HOLDA goes low when the port is placed in the high impendance state STRB0 control register only SWW 11 Software wait mode In conjunction with WTCNT this 2 bit field defi...

Page 314: ...value if PRGW 0 Setting the physical memory width field of the STRB0 or STRB1 control registers changes the functionality of the STRB0 or STRB1 signals When the physical memory width field is configured to 32 bits the corresponding STRBx_B0 STRBx_B3 signals are configured as byte enable pins see Figure 10 10 on page 10 20 When the physical memory width field is configured to 16 bits the correspond...

Page 315: ...an have the following values Bit 21 Physical Memory Width 0 STRB0_Bx signals are active for locations 0h 7FFFFFh and 880000h 8FFFFFh STRB1_Bx signals are active for locations 900000h FFFFFFh reset value 1 STRB0_Bx signals are active for locations 0h 7FFFFFh 880000h 8FFFFFh and 900000h FFFFFFh STRB1_Bx signals are active for locations 900000h FFFFFFh A functional representation of this configuratio...

Page 316: ...e the banks are separate memories Note that C32 address pins A23A22A21 A1A0 are connected to the STRB0 memory bank address pins A23A22A21 A1A0 But C32 address pins A22A21 A1A0 A 1 are connected to the STRB1 memory bank address pins A23A22A21 A1A0 Executing the following code on this device results in the data access sequence shown in Table 10 2 ÁÁ ÁÁ ÁÁ ÁÁ ÁÁ ÁÁ ÁÁ ÁÁ ÁÁ 1 2 3 4 5 6 7 8 9 ÁÁÁÁ ÁÁÁ...

Page 317: ...ÁÁ ÁÁÁÁÁÁÁÁÁ STRB0_B0 B1 B2 B3 ÁÁÁÁ ÁÁÁÁ D31 0 ÁÁÁÁ ÁÁÁÁ 4001h ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ 4 ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ 4002h ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ 4002h ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ STRB0_B0 B1 B2 B3 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ D31 0 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ 4002h ÁÁÁÁÁÁ ÁÁÁÁÁÁ 5 ÁÁÁÁÁÁ ÁÁÁÁÁÁ 4003h ÁÁÁÁÁÁ ÁÁÁÁÁÁ 4003h ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ STRB0_B0 B1 B2 B3 ÁÁÁÁ ÁÁÁÁ D31 0 ÁÁÁÁ ÁÁÁÁ 4003h ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ 8 ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ...

Page 318: ...re used to generate the internal ready signal RDYint that controls accesses As long as RDYint 1 the current external access is delayed When RDYint 0 the current access completes Since the use of programmable wait states for both external interfaces is identical only the primary bus interface is described in the following paragraphs RDYwtcnt is an internally generated ready signal When an external ...

Page 319: ...x 0 1 Wait until external RDY is signaled 01 x x 0 1 0 1 Wait until internal wait state generator counts down to 0 10 0 0 1 1 0 1 0 1 0 0 0 1 Wait until first signal external RDY or the internal wait state generator logical OR 11 0 0 1 1 0 1 0 1 0 1 1 1 Wait until both external RDY is signaled and wait state generator counts down to 0 logical AND ...

Page 320: ... size is specified by the eight LSBs yielding a bank size of 256 words If BNKCMP 16 only the 16 MSBs are compared Bank sizes from 28 256 to 224 16M are allowed Table 9 6 summarizes the relationship between BNKCMP the address bits used to define a bank and the resulting bank size Figure 10 8 BNKCMP Example 23 8 7 0 24 bit address Number of bits to compare Defines bank size Table 10 4 BNKCMP and Ban...

Page 321: ... being used for the current read of the current address If the MSBs of the address being used for the current read match the bits in the register a normal read cycle takes place If repeated reads are performed from the same memory bank no extra cycles are inserted When a read is performed from a different memory bank memory conflicts are avoided by the insertion of an extra cycle This feature can ...

Page 322: ...Programmable Bank Switching 10 19 TMS320C32 Enhanced External Memory Interface Note After changing BNKCMP up to three instructions are fetched before the change in bank size occurs ...

Page 323: ...7 0 AXX WE CS I O 7 0 AXX WE CS I O 7 0 AXX WE CS I O 7 0 AXX WE CS I O 7 0 C32 Case 1 32 Bit Wide Memory With 8 Bit Data Type Size When the data type size is 8 bits the C32 shifts the internal address two bits to the right before presenting it to the external address pins In this shift the memory interface copies the value of the internal address A23 to the external address pins A23 A22 and A21 T...

Page 324: ...ÁÁÁÁ ÁÁÁÁÁ 1 ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ STRBx_B1 ÁÁÁÁ ÁÁÁÁ 1 ÁÁÁÁÁ ÁÁÁÁÁ 0 ÁÁÁÁÁ ÁÁÁÁÁ STRBx_B2 ÁÁÁÁ ÁÁÁÁ 1 ÁÁÁÁÁ ÁÁÁÁÁ 1 ÁÁÁÁÁ ÁÁÁÁÁ STRBx_B3 Figure 10 11 Functional Diagram for 8 Bit Data Type Size and 32 Bit External Memory Width A21 A20 A19 A18 A0 CS I O 7 0 C32 A 23 A 22 A 21 A 20 A 19 A 18 A 0 D 31 24 D 23 16 D 15 8 D 7 0 A21 A20 A19 A18 A0 CS I O 7 0 A21 A20 A19 A18 A0 CS I O 7 0 A21 A20 A19 A18 A0 ...

Page 325: ...ÁÁÁÁ 904004h ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ E41001h ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ STRB1_B0 ÁÁÁÁ ÁÁÁÁ D7 0 Case 2 32 Bit Wide Memory With 16 Bit Data Type Size When the data type size is 16 bits the C32 shifts the internal address one bit to the right before presenting it to the external address pins In this shift the memory interface copies the value of the internal address A23 to the external address pins A23 and A22 Also ...

Page 326: ...ins listed in Table 10 8 Table 10 8 Example of 16 Bit Data Type Size and 32 Bit Wide External Memory ÁÁÁÁÁ ÁÁÁÁÁ Internal Address Bus ÁÁÁÁÁÁ ÁÁÁÁÁÁ External Address Pins ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Active Strobe Byte Enable ÁÁÁÁÁ ÁÁÁÁÁ Accessed Data Pins ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ 904000h ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ C82000h ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ STRB1_B1 and STRB1_B0 ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ D15 0 ÁÁÁÁÁ ÁÁÁÁÁ 90400...

Page 327: ... during accesses Figure 10 13 shows a functional diagram of the memory interface for 32 bit wide memory with 32 bit data size Figure 10 13 Functional Diagram for 32 Bit Data Size and 32 Bit External Memory Width A23 A22 A21 A20 A2 A1 A0 CS I O 7 0 C32 A23 A22 A21 A20 A2 A1 A0 D 31 24 D 23 16 D 15 8 D 7 0 Memoryinterface A23 A22 A21 A20 A2 A1 A0 CS I O 7 0 A23 A22 A21 A20 A2 A1 A0 CS I O 7 0 A23 A2...

Page 328: ...ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ STRB1_B0 STRB1_B1 STRB1_B2 and STRB1_B3 ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ D31 0 ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ 904001h ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ 904001h ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ STRB1_B0 STRB1_B1 STRB1_B2 and STRB1_B3 ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ D31 0 ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ 904002h ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ 904002h ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ STRB1_B0 STRB1_B1 STRB1_B2 and STRB1_B3 ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ D31 0 ÁÁÁÁÁ...

Page 329: ...I O 7 0 A23 A22 A2 A1 A0 WE CS I O 7 0 C32 STRBx_B2 STRBx_B1 STRBx_B0 D 31 24 D 23 16 D 15 8 D 7 0 Case 4 16 Bit Wide Memory With 8 Bit Data Type Size When the data type size is 8 bits the C32 shifts the internal address two bits to the right before presenting it to the external address pins In this shift the memory interface copies the value of the internal address A23 to the external address pin...

Page 330: ...ÁÁÁÁÁ STRBx_B0 ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ 1 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ STRBx_B1 Figure 10 15 Functional Diagram for 8 Bit Data Type Size and 16 Bit External Memory Width A22 A21 A20 A19 A1 A0 CS I O 7 0 A22 A21 A20 A19 A1 A0 CS I O 7 0 C32 A23 A22 A21 A20 A19 A18 A0 STRBx_B3 A 1 STRBx_B1 STRBx_B0 D 15 8 D 7 0 A23 A22 A21 A20 A2 A1 A0 1 0 Memoryinterface C32 s core address b...

Page 331: ...Á ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 4003h ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ 1000h ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ 1 ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ STRB0_B1 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ D15 8 ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 4004h ÁÁÁÁÁ ÁÁÁÁÁ 1001h ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ 0 ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ STRB0_B0 ÁÁÁÁ ÁÁÁÁ D7 0 Case 5 16 Bit Wide Memory With 16 Bit Data Type Size When the data type size is 16 bits the C32 shifts the internal address one bit to the right before pr...

Page 332: ...ernal Address Bus ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ External Address Pins ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ STRB0_B3 A 1 ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Active Strobe Byte Enable ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ Accessed Data Pins ÁÁÁÁÁÁ ÁÁÁÁÁÁ 4000h ÁÁÁÁÁÁ ÁÁÁÁÁÁ 2000h ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 0 ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ STRB0_B0 and STRB0_B1 ÁÁÁÁÁ ÁÁÁÁÁ D15 0 ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ 4001h ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ 2000h ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1 ÁÁÁÁÁÁ...

Page 333: ... interface activates STRBx_B1 and STRBx_B0 In summary the memory interface seems to add one wait state to the 32 bit data access Figure 10 17 depicts a functional diagram of the memory interface for 16 bit wide memory with 32 bit data type size Figure 10 17 Functional Diagram for 32 Bit Data Type Size and 16 Bit External Memory Width STRBx_B3 A 1 STRBx_B1 STRBx_B0 A24 A23 A22 A21 A3 A2 A1 A0 CS I ...

Page 334: ... ÁÁÁÁÁÁÁÁÁÁ STRB0_B0 and STRB0_B1 ÁÁÁÁÁÁ ÁÁÁÁÁÁ D15 0 ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ 4001h ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1 ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ STRB0_B0 and STRB0_B1 ÁÁÁÁÁÁ ÁÁÁÁÁÁ D15 0 ÁÁÁÁÁ ÁÁÁÁÁ 4002h ÁÁÁÁÁÁ ÁÁÁÁÁÁ 4002h ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 0 ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ STRB0_B0 and STRB0_B1 ÁÁÁÁÁÁ ÁÁÁÁÁÁ D15 0 ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ 4002h ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1 ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ STRB0_B0 and STRB0_B1 ÁÁÁÁÁÁ ÁÁÁÁÁÁ D15 ...

Page 335: ...I O 7 0 C32 STRBx_B1 STRBx_B0 D 31 24 D 23 16 D 15 8 D 7 0 STRBx_B3 A 1 A1 Case 7 8 Bit Wide Memory With 8 Bit Data Type Size Similarly to case 4 the C32 shifts the internal address two bits to the right before presenting it to the external address pins when the data type is 8 bit As in case 4 the memory interface copies the value of the internal address A23 to the external address pins A23 A22 an...

Page 336: ...ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ External Address Pins ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ STRB0_B3 A 1 ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ STRB0_B3 A 2 ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ Active Strobe Byte Enable ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ Accessed Data Pins ÁÁÁÁÁÁ ÁÁÁÁÁÁ A04000h ÁÁÁÁÁÁ ÁÁÁÁÁÁ E81000h ÁÁÁÁÁÁ ÁÁÁÁÁÁ 0 ÁÁÁÁÁÁ ÁÁÁÁÁÁ 0 ÁÁÁÁÁÁ ÁÁÁÁÁÁ STRB1_B0 ÁÁÁÁÁ ÁÁÁÁÁ D7 0 ÁÁÁÁÁÁ ÁÁÁÁÁÁ A04001h ÁÁÁÁÁÁ ÁÁÁÁÁÁ E81000h ÁÁÁÁÁÁ ÁÁÁÁÁÁ 0 ÁÁÁÁÁÁ ÁÁÁÁÁÁ 1 ÁÁÁÁÁÁ ÁÁÁÁÁÁ ...

Page 337: ... 1 pin Furthermore the memory interface toggles STRBx_B2 A 2 twice to perform two 8 bit memory accesses Moreover the memory interface activates the STRBx_B0 during accesses In summary the memory interface adds one wait state to the 16 bit data access Figure 10 20 shows a functional diagram of the memory inter face for 8 bit wide memory with 16 bit data type size Figure 10 20 Functional Diagram for...

Page 338: ...ÁÁÁÁ 1 1 ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ 0 1 ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ STRB1_B0 STRB1_B0 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ D7 0 D7 0 ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ A04002h ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ D02002h D02002h ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ 0 0 ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ 0 1 ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ STRB1_B0 STRB1_B0 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ D7 0 D7 0 Case 9 8 Bit Wide Memory With 32 Bit Data Type Size When the data type size is 32 bits the C32 does not shift the internal ad...

Page 339: ...ram for 32 Bit Data Type Size and 8 Bit External Memory Width A24 A23 A22 A4 A2 A1 A0 CS I O 7 0 C32 A23 A22 A21 A20 A1 A0 STRBx_B3 A 1 STRBx_B0 D 7 0 A23 A22 A21 A20 A2 A1 A0 Memoryinterface toggle STRBx logic STRBx_B2 A 2 toggle A25 A3 A1 C32 s core address bus ...

Page 340: ... ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ A04000h ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ 0 ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1 ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ STRB1_B0 ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ D7 0 ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ A04000h ÁÁÁÁÁÁ ÁÁÁÁÁÁ 1 ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 0 ÁÁÁÁÁÁ ÁÁÁÁÁÁ STRB1_B0 ÁÁÁÁÁ ÁÁÁÁÁ D7 0 ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ A04000h ÁÁÁÁÁÁ ÁÁÁÁÁÁ 1 ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1 ÁÁÁÁÁÁ ÁÁÁÁÁÁ STRB1_B0 ÁÁÁÁÁ ÁÁÁÁÁ D7 0 ÁÁÁÁÁ ÁÁÁÁÁ A04001h ÁÁÁÁÁÁ ÁÁÁÁÁÁ A04001h ÁÁÁÁÁÁ ÁÁÁ...

Page 341: ...lent to the C4x ready timing which increases the time between valid address and the sampling of RDY This facilitates the memory hardware interface by allowing a longer address decode circuit response time to generate a ready signal Figure 10 22 RDY Timing for Memory Read RDY D A R W STRBx H1 H3 Data Address tsu RDY Do not change the RDY signal during its setup time tsu RDY ...

Page 342: ...ne cycle if no other accesses to that interface are in progress The following discussion pertains to zero wait state accesses unless otherwise specified The STRBx signal is low for the active portion of both reads and writes one H1 cycle Additionally before and after the active portions of writes only STRBx low there is a transition of one H1 cycle During this transition cycle the following might ...

Page 343: ...0 24 shows a zero wait state write write read sequence for STRBx active During back to back writes the data is valid when STRBx changes for the first write but for subsequent writes the data is valid when the address changes Figure 10 24 Write Write Read Sequence for STRBx Active RDY D A R W STRBx H1 H3 Write Write Read ...

Page 344: ... 26 shows the write sequence for STRBx active On the first H1 cycle RDYis high therefore the read or write sequence is extended for one extra cycle On the second H1 cycle RDY is low and the read or write sequence is terminated Figure 10 25 One Wait State Read Sequence for STRBx Active STRBx RDY D A R W H1 H3 Extra cycle Read ...

Page 345: ... H1 cycles During these cycles the IOSTRB signal is low from the rising edge of the first H1 cycle to the rising edge of the second H1 cycle Also the address changes on the falling edge of the first H1 cycle and R W changes state on the falling edge of H1 This provides a valid address to peripherals that may change their status bits when read or written while IOSTRB is active Moreover the IOSTRB s...

Page 346: ... and Write Sequence for IOSTRB Active Write Read IOSTRB RDY D A R W H1 H3 Figure 10 28 depicts a one wait state read sequence for IOSTRB active Figure 10 29 shows a one wait state write sequence for IOSTRB active For each wait state added IOSTRB R W and A are extended for one extra clock cycle Writes hold the data on the bus for one extra clock cycle RDY is sampled on each extra cycle and the sequ...

Page 347: ...cycle Read Figure 10 29 One Wait State Write Sequence for IOSTRB Active IOSTRB RDY D A R W H1 H3 Extra cycle Write Figure 10 30 and Figure 10 31 illustrate the transitions between STRBx reads and IOSTRB writes and reads respectively In these transitions the ad dress changes on the falling edge of the H1 cycle ...

Page 348: ...MS320C32 Enhanced External Memory Interface Figure 10 30 STRBx Read and IOSTRB Write I O Write Read STRB0 1 IOSTRB RDY D A R W H1 H3 Figure 10 31 STRBx Read and IOSTRB Read I O read Read STRB0 1 IOSTRB RDY D A R W H1 H3 ...

Page 349: ...s and IOSTRB writes and reads respectively In these transitions the address changes on the falling edge of the H3 cycle Figure 10 32 STRBx Write and IOSTRB Write Write I O write STRBx IOSTRB RDY D A R W H1 H3 Figure 10 33 STRBx Write and IOSTRB Read Write STRBx IOSTRB RDY D A R W H1 H3 I O read ...

Page 350: ...ure 10 34 through Figure 10 37 show the transitions between IOSTRB writes reads and STRBx writes reads In these transitions the address changes on the rising edge of the H3 cycle Figure 10 34 IOSTRB Write and STRBx Write I O write Write STRBx IOSTRB RDY D A R W H1 H3 ...

Page 351: ...Bus Timing 10 48 Figure 10 35 IOSTRB Write and STRBx Read I O Write Read STRBx IOSTRB RDY D A R W H1 H3 Figure 10 36 IOSTRB Read and STRBx Write I O read Write STRBx IOSTRB RDY D A R W H1 H3 ...

Page 352: ...9 TMS320C32 Enhanced External Memory Interface Figure 10 37 IOSTRB Read and STRBx Read Read I O Read STRBx IOSTRB RDY D A R W H1 H3 Figure 10 38 through Figure 10 40 illustrate the transitions between reads and writes ...

Page 353: ...Bus Timing 10 50 Figure 10 38 IOSTRB Write and Read I O write IOSTRB RDY D A R W H1 H3 I O read Figure 10 39 IOSTRB Write and Write I O write I O write IOSTRB RDY D A R W H1 H3 ...

Page 354: ...1 and Figure 10 42 show the signal states when a bus becomes inactive after an IOSTRB or STRBx respectively The strobes STRB0 STRB1 IOSTRB and R W are deasserted going to a high level The address bus preserves the last value and the ready signal RDY is ignored Figure 10 41 Inactive Bus States Following IOSTRB Bus Cycle I O Write IOSTRB RDY D A R W H1 H3 Bus inactive RDY ignored ...

Page 355: ...Bus Timing 10 52 Figure 10 42 Inactive Bus States Following STRBx Bus Cycle I O write STRBx RDY D A R W H1 H3 Bus inactive RDY ignored ...

Page 356: ...The C31 and C32 have on chip boot loaders that can load and execute pro grams received from a host processor standard memory devices including EPROM or via serial port Topic Page 11 1 TMS320C31 Boot Loader 11 2 11 2 TMS320C32 Boot Loader 11 14 Chapter 11 ...

Page 357: ... ROM The source code is supplied in Appendix B 11 1 2 TMS320C31 Boot Loader Mode Selection The C31 boot loader functions as a memory boot loader or a serial port boot loader The boot loader function is selected by resetting the processor while driving the MCBL MP pin high Use interrupt pins INT3 INT0 to select the boot load operation Figure 11 1 shows the flow of this operation which depends on th...

Page 358: ...ternal memory Boot 2 address 0x400000 1 1 0 1 External memory Boot 3 address 0xFFF000 1 1 1 0 32 bit serial Serial port 0 Figure 11 1 TMS320C31 Boot Loader Mode Selection Flowchart No Yes No Yes MCBL MP 1 Reset Begin Serial port load No Yes Yes No register bit INT3 set register bit INT0 set register bit INT1 set register bit INT2 set Memory load from 1000h Memory load from 400000h Memory load from...

Page 359: ...rial port must begin with the most significant bit MSB and end with the least significant bit LSB Figure 11 3 depicts the boot loader serial port flow 4 Otherwise the boot loader attempts a memory boot load Figure 11 2 shows the boot loader memory flow If the IF register s INT0 bit field is set the source program is loaded from memory location 1000h If the IF register s INT1 bit field is set the s...

Page 360: ...st Branch to destination Load next block size Block size 1 Transfer data from source to destination Yes Yes address Load destination Load block size control word configuration Set memory Determine mode 8 16 or 32 boot 3 boot 2 or boot 1 Branch to address No No Block size 0 Begin program execution Memory load End of source program code block size 0 ...

Page 361: ...e Flowchart Begin program execution Block size 1 Transfer data from serial port to destination address port input Wait for serial Load destination address port input Wait for serial Block size 0 No Yes block loaded address of first Branch to destination Yes No Block size 0 ...

Page 362: ...his header to determine the physical memory width where the source program resides memory load and to configure the primary bus interface before source program boot load The blocks of source data have two entries in addition to the raw data The first entry in this block indicates the size of the block The second entry in this block indicates the memory address where the boot loader copies this sou...

Page 363: ...it wide data value m Size of last data block The block size is the number of 32 bit words in the data block If the next word following this block is not 0 another block is loaded 0 size 224 m 1 Destination address to load the last block A valid C31 24 bit address m 2 First word of last block A C31 valid instruction or any 32 bit wide data value LSB first j Last word of last source block ÁÁÁÁ ÁÁÁÁ ...

Page 364: ...er resides at memory location 0x1000 and defines the following J Boot memory type EPROMs that require two wait states and SWW 11 J A loader destination address at the beginning of the C31 internal RAM block 1 J A single block of memory that is 0x1FF in length Table 11 3 Byte Wide Configured Memory Address Value Comments 0x1000 0x08 Memory width 8 bits 0x1001 0x00 0x1002 0x00 0x1003 0x00 0x1004 0x5...

Page 365: ...809C00 Program load starting address 0x809C00 After reading the header the loader transfers 0x IFF 32 bit words beginning at a specified destination address 0x 809C00 Code blocks require the same byte and half word ordering conventions The loader can also load multiple code blocks at different address destinations After loading all code blocks the boot loader branches to the destination address of...

Page 366: ...order must begin with the MSB and end with the LSB 11 1 5 Interrupt and Trap Vector Mapping Unlike the microprocessor mode the microcomputer boot loader MCBL mode uses a dual vectoring scheme to service interrupt and trap requests Dual vectoring was implemented to ensure code compatibility with future versions of C3x devices In a dual vectoring scheme branch instructions to an address rather than ...

Page 367: ...mory Maps Address Description 809FC1 INT0 809FC2 INT1 809FC3 INT2 809FC4 INT3 809FC5 XINT0 809FC6 RINT0 809FC7 XINT1 Reserved 809FC8 RINT1 Reserved 809FC9 TINT0 809FCA TINT1 809FCB DINT0 809FCC 809FDF Reserved 809FE0 TRAP0 809FE1 TRAP1 809FFB TRAP27 809FFC 809FFF Reserved ...

Page 368: ... function If pending interrupts are to be avoided when interrupts are enabled clear the IF register before enabling interrupts The MCBL MP pin must remain high during the entire boot loader execution but it can be changed subsequently at any time The C31 does not need to be reset after the MCBL MP pin is changed During the change the C31 must not access addresses 0h FFFh The memory space 0h FFFh w...

Page 369: ...urce code is supplied in Appendix C 11 2 2 TMS320C32 Boot Loader Mode Selection The C32 boot loader functions as a memory boot loader memory boot loader with handshake or a serial port boot loader The boot loader mode selection is determined by the status of the INT3 INT0 pins immediately following reset Table 11 7 lists the boot loader modes The memory boot loader supports user definable byte hal...

Page 370: ...ng 11 2 3 TMS320C32 Boot Loading Sequence The following is the sequence of events that occur during the boot load of a source program Table 11 2 shows the structure of the source program 1 Select the boot loader by resetting the C32 while driving the MCBL MP pin high and the corresponding INT3 INT0 pins low The MCBL MP must stay high during boot loading but can be changed anytime after boot loadin...

Page 371: ...s to the host that the data was read c The host sets XF1 high to inform the C32 that the data is no longer valid d The C32 terminates the transfer by setting XF0 high The memory boot load source program has a header indicating the boot memory width and the contents of the STRB0 STRB1 and IOSTRB control registers see Table 11 2 5 After reading the header the boot loader copies the source program bl...

Page 372: ...4 TMS320C32 Boot Loader Mode Selection Flowchart No Yes No Yes MCBL MP 1 Reset Begin Serial port load No Yes Yes No register bit INT3 set register bit INT1 set register bit INT0 set register bit INT2 set Memory load from 81000h Memory load from 1000h Memory load from 900000h Is Is Is Is ...

Page 373: ... Serial port load Yes No Set up serial port for 32 bit fixed burst mode Read IOSTRB control word Wait for serial port Input Wait for serial port Input Read STRB0 control word Wait for serial port Input Read STRB1 control word Wait for serial port Input Load block size Wait for serial port input Set STRB0 STRB1 and IOSTRB control registers Load destination address Wait for serial port input Read de...

Page 374: ...tion address Read destination strobe control word Read destination address Read STRB0 control register Read IOSTRB control register Read memory width 8 16 or 32 bits Determine boot address Boot 1 Boot 2 or Boot 3 Read STRB1 control register According to the destination address set corresponding STRB control register to the previously read value Is IF register bit field INT3 set Memory load Yes No ...

Page 375: ...ides memory load and to configure the STRBs after completion of source program boot load The blocks of source data have three entries in addition to the raw data The first entry in this block indicates the size of the block The second entry in this block indicates the memory address where the boot loader copies this source block The third entry contains the destination memory strobe configuration ...

Page 376: ... 5 Size of the first data block The block size is the number of words in the data block word length is specified by the data type size A 0 in this entry signifies the end of the source data stream 0 size 224 6 Destination address to load the first block A valid C32 24 bit address 7 First block destination memory width and data type size in the format given in the Valid Data Entries column SSSSSS6x...

Page 377: ...s not reside in memory The SSSSSS hexadecimal digits refer to the lower 24 bits of the strobe control register The x hexadecimal digit identifies the strobe as follows 0 for IOSTRB 4 for STRB0 and 8 for STRB1 SSSSSS6xh is cleared to 0 when loading the entire field into internal memory Each source block can be loaded into a different memory location Each block specifies its own size and destination...

Page 378: ...t Load C32 STRBX_B3 STRBX_B2 STRBX_B1 STRBX_B0 D 31 24 D 23 16 D 15 8 D 7 0 I O 7 0 A23 A22 A21 A20 A2 A1 A0 A23 A22 A21 A20 A2 A1 A0 CS I O 7 0 A23 A22 A21 A20 A2 A1 A0 CS I O 7 0 A23 A22 A21 A20 A2 A1 A0 CS I O 7 0 A23 A22 A21 A20 A2 A1 A0 CS 16 bit wide EPROM 32 bit wide EPROM 8 bit wide EPROM 11 2 6 TMS320C32 Boot Loader Precautions The interrupt flags are not reset by the boot loader function...

Page 379: ... counter register 808024h Timer0 period register 808028h DMA0 source address register 808004h DMA0 destination address register 808006h DMA0 transfer counter register 808008h These memory mapped registers are not reset by the boot loading process Before using these peripherals reprogram these registers with the appropriate values ...

Page 380: ...peripheral bus The DMA controller performs input output operations without interfering with the operation of the CPU making it possible to interface the C3x to slow exter nal memories and peripherals analog to digital converters A Ds serial ports and so forth without reducing the computational throughput of the CPU The result is improved system performance and decreased system cost Topic Page 12 1...

Page 381: ...h timer has an I O pin that you can use as an input clock to the timer as an output clock signal or as a general purpose I O pin Each timer consists of a 32 bit counter a comparator an input clock selector a pulse generator and supporting hardware see Figure 12 1 A timer counts the cycles of a timer input clock with the counter register When that counter register equals the value stored in the tim...

Page 382: ...etermines the operating mode of the timer monitors the timer status and controls the function of the I O pin of the timer Period register The period register specifies the timer s signaling frequency Counter register The counter register contains the current value of the incrementing counter You can increment the timer on the rising edge or the falling edge of the input clock The counter is zeroed...

Page 383: ...ol bits for the timer module Figure 12 3 shows the format of the timer global control register Bits 3 0 are the port control bits bits 11 6 are the timer global control bits At reset all bits are set to 0 except for DATIN which is set to the value read on TCLK Table 12 1 describes the timer global control register bits their names and functions Figure 12 3 Timer Global Control Register 31 16 15 12...

Page 384: ...Resets and starts the timer counter When GO 1 and the timer is not held the counter is zeroed and begins incrementing on the next rising edge of the timer input clock The GO bit is cleared on the same rising edge GO 0 has no effect on the timer HLD 0 Counter hold signal When this bit is 0 the counter is disabled and held in its current state If the timer is driving TCLK the state of TCLK is also h...

Page 385: ...nchronized internally thus allowing external asynchronous clock sources that do not ex ceed the specified maximum allowable external clock frequency This is less than f H1 2 See section 12 1 6 Timer Operation Modes on page 12 10 for a description of the relationship be tween FUNC and CLKSRC INV 0 Inverter control bit If an external clock source is used and INV 1 the external clock is inverted as i...

Page 386: ...the period register 0 the counter counts rolls over to 0 and behaves as described above When the counter register is set to a value greater than the period register the counter may overflow when incremented Once the counter reaches its maximum 32 bit value 0FFFFFFFFh it rolls over to 0 and continues Writes from the peripheral bus override register updates from the counter and new status updates to...

Page 387: ...T The timer signaling is determined by the frequency of the timer input clock and the period register The following equations are valid with either an internal or an external timer clock f pulse mode f timer clock period register f clock mode f timer clock 2 x period register Note Period register If the period register equals 0 see Section 12 1 4 Example 12 1 provides some examples of the TCLKx ou...

Page 388: ...se mode timer period 1 Also 4H1 H1 b INV 0 C P 0 pulse mode timer period 2 6H1 H1 c INV 0 C P 0 pulse mode timer period 3 4H1 d INV 0 C P 1 clock mode timer period 1 8H1 4H1 e INV 0 C P 1 clock mode timer period 2 12H1 6H1 f INV 0 C P 1 clock mode timer period 3 INV 0 C P 1 clock mode timer period 0 ...

Page 389: ...a general purpose I O pin see Figure 12 5 If I O 0 TCLK is configured as a general purpose input pin whose state you can read in DATIN DATOUT has no effect on TCLK or DATIN See Figure 12 5 a If I O 1 TCLK is configured as a general purpose output pin DATOUT is placed on TCLK and can be read in DATIN See Figure 12 5 b Figure 12 5 Timer Configuration with CLKSRC 1 and FUNC 0 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ...

Page 390: ...is driven according to the status of the I O bit If I O 0 the timer input comes from TCLK This value can be inverted using INV and you can read in DATIN the value of TCLK See Figure 12 7 a If I O 1 TCLK is an output pin Then TCLK and the timer are both driven by DATOUT All 0 to 1 transitions of DATOUT increment the counter INV has no effect on DATOUT You can read in DATIN the value of DATOUT See F...

Page 391: ...7 Using TCLKx as General Purpose I O Pins When FUNC 0 TCLKx can be used as an I O pin Figure 12 9 and Figure 12 10 show how the TCLKx is connected when it is configured as a general purpose I O pin In Figure 12 9 the I O bit equals 0 and TCLK is configured as an input pin whose value can be read in the DATIN bit In Figure 12 10 the I O bit equals 1 and TCLK is configured as an output pin that outp...

Page 392: ...rrupt enable control for each timer for either the CPU or the DMA is found in the CPU DMA interrupt enable register Refer to Section 3 1 8 CPU DMA Interrupt Enable Register IE on page 3 9 for more information When a timer interrupt occurs a change in the state of the corresponding TCLK pin is observed if FUNC 1 and CLKSRC 1 in the timer global control register The exact change in the state depends...

Page 393: ...ency through the TCLKx pin Example 12 2 Maximum Frequency Timer Clock Setup Maximum Frequency Timer Clock Setup data Timer0 word 808020h Timer global control address TCTRL_RST word 301h TCTRL_GD word 3C1h TCNT word 0 Timer counter value TPRD word 0 Timer period value text LDP Timer0 LD1 Timer0 AR0 Load data page pointer LD1 0 R0 ST1 R0 AR0 Halt timer LD1 TCTRL_RST R0 Configure timer ST1 R0 AR0 LD1...

Page 394: ...ort to transmit and receive any number of words without new synchronization pulses Eight memory mapped registers are provided for each serial port Global control register Two control registers for the six serial I O pins Three receive transmit timer registers Data transmit register Data receive register The global control register controls the global functions of the serial port and determines the...

Page 395: ...ceive Section Transmit Section Receive timer 16 Transmit timer 16 Bit counter 8 16 24 32 Bit counter 8 16 24 32 RSR 32 XSR 32 DRR 32 DXR 32 Load control Load control CLKR CLKX TSTAT CLKR CLKX TSTAT Receive Clock RINT FSR FSR FSX FSX Load DX DR DR Load DX DX XINT ...

Page 396: ...LKR control Serial port 1 R X timer control Serial port 1 R X timer counter Serial port 1 R X timer periodk Serial port 1 data transmitl Serial port 1 data receivej 808050h 808052h 808053h 808054h 808055h 808056h 808058h 80805Ch Note Serial port1 locations are reserved on the C31 and C32 See Figure 12 13 See Figure 12 14 See Figure 12 15 See Figure 12 16 See Figure 12 17 See Figure 12 18 kSee Figu...

Page 397: ...e shifter and is ready for a new word A three H1 H3 cycle delay occurs from the loading of the transmit shifter until XRDY is set to 1 The rising edge of this signal sets XINT If XRDY 0 the transmit buffer has not written the last bit of data to the transmit shifter and is not ready for a new word FSXOUT Transmit frame sync configuration FSXOUT 0 configures the FSX pin as an input FSXOUT 1 configu...

Page 398: ...ransmitter when FSX is held active or when a word is being shifted out RVAREN 0 Receive data rate mode Specifies a fixed or variable data rate mode when receiving If RVAREN 0 fixed data rate FSX is active for at least one RCLK cycle and then goes inactive before reception begins If RVAREN 1 controlled data rate FSX is active while all bits are being received XFSM 0 Transmit frame sync mode Configu...

Page 399: ... buffer when fewer than 32 bits are specified 0 0 8 bits 1 0 24 bits 0 1 16 bits 1 1 32 bits RLEN 00 Receive word length These two bits define the word length of serial data received All data is right justified in the receive buffer 0 0 8 bits 1 0 24 bits 0 1 16 bits 1 1 32 bits XTINT 0 Transmit timer interrupt enable If XTINT 0 the transmit timer interrupt is disabled If XTINT 1 the transmit time...

Page 400: ...SET to 0 does not change the contents of any of the serial port control registers It places the transmitter in a state corresponding to the beginning of a frame of data Resetting the transmitter generates a transmit interrupt Reset this bit during the time the mode of the transmitter is set You can toggle XFSM without resetting the global control register RRESET 0 Receive reset If RRESET 0 the rec...

Page 401: ...I O port If CLKX FUNC 1 CLKX is configured as a serial port pin CLKX I O 0 Clock transmit input output mode If CLKX I O 0 CLKX is configured as a general purpose input pin If CLKX I O 1 CLKX is configured as a general purpose output pin CLKX DATOUT 0 Clock transmit data ouput Data output on CLKX when configured as general purpose output CLKX DATIN x Clock transmit data input Data input on CLKX whe...

Page 402: ... when configured as general purpose output FSX DATIN x FSX data input Data input on FSX when configured as general purpose input A write has no effect x 0 or 1 12 2 3 FSR DR CLKR Port Control Register This 32 bit port control register is controlled by the function of the FSR DR and CLKR pins At reset all bits are set to 0 The register is shown in Figure 12 15 Table 12 4 shows the register bits bit...

Page 403: ...ed as a general purpose digital I O port If DR FUNC 1 DR is configured as a serial port pin DR I O 0 DR input output mode If DR I O 0 DR is configured as a general purpose input pin If DR I O 1 DR is configured as a general purpose output pin DR DATOUT 0 DR data output Data output on DR when configured as general purpose output DR DATIN x DR data input Data input on DR when configured as general p...

Page 404: ... 2 xx reserved bit read as 0 Table 12 5 Receive Transmit Timer Control Register Register Bits Summary Abbreviation Reset Value Name Function XGO 0 Transmit timer counter restart Resets and restarts the transmit timer counter If XGO 1 and the timer is not held the counter is zeroed and begins incrementing on the next rising edge of the timer input clock The XGO bit is cleared on the same rising edg...

Page 405: ... CLKX pin This flag sets a CPU interrupt on a transition from 0 to 1 A write has no effect RGO 0 Receive timer counter restart Resets and starts the receive timer counter When RGO is set to 1 and the timer is not held the counter is zeroed and begins incrementing on the next rising edge of the timer input clock The RGO bit is cleared on the same rising edge Writing 0 to RGO has no effect on the re...

Page 406: ... speci fied maximum allowable external clock frequency that is less than f H1 2 6 RTSTAT 0 Receive timer status Indicates the status of the receive timer It tracks what would be the output of the uninverted CLKR pin This flag sets a CPU interrupt on a transition from 0 to 1 A write has no effect 12 2 5 Receive Transmit Timer Counter Register The receive transmit timer counter register is a 32 bit ...

Page 407: ...ur tap points within the transmit shift register are used to transmit the word These tap points correspond to the four data word sizes and are illustrated in Figure 12 19 The shift is a left shift LSB to MSB with the data shifted out of the MSB corresponding to the appropriate tap point Figure 12 19 Transmit Buffer Shift Operation 31 24 23 16 15 8 7 0 32 bit word tap 24 bit word tap 16 bit word ta...

Page 408: ... register is read both bytes a and b are read Figure 12 20 Receive Buffer Shift Operation After byte a After byte b 31 24 23 16 15 8 7 0 X X X a X X a b Shift direction 12 2 9 Serial Port Operation Configurations Several configurations are provided for the operation of the serial port clocks and timer The clocks for each serial port can originate either internally or exter nally Figure 12 21 shows...

Page 409: ...UNC 0 I O mode CLKX I O 0 CLKX an input XCLK SRC 1 internal CLK for timer c CLKX FUNC 0 I O mode CLKX I O 0 CLKX an input XCLK SRC 0 external CLK for timer d CLKX FUNC 0 I O mode CLKX I O 1 CLKX an output XCLK SRC 1 internal CLK for timer CLKX FUNC 0 I O mode CLKX I O 1 CLKX an output XCLK SRC 0 external CLK for timer External Internal External Internal External Internal External Internal clock In...

Page 410: ...ncy of the serial port clock with an inter nally generated clock depends upon the operation mode of the serial port timers defined as f pulse mode f timer clock period register f clock mode f timer clock 2 x period register An internally generated clock source f timer clock has a maximum frequency of f H1 2 An externally generated serial port clock f timer clock CLKX or CLKR has a maximum frequenc...

Page 411: ...e data rate is specified the FSX pin is activated when the data transmission begins and remains active during the entire transmission of the word Again the data is transmitted one clock cycle after it is loaded into the data transmit register An input FSX in the fixed data rate mode must go active for at least one serial clock cycle and then inactive to initiate the data transfer The transmitter t...

Page 412: ... terminate the receive continuous mode 12 2 10 2 Handshake Mode The handshake mode HS 1 allows for direct connection between processors In this mode all data words are transmitted with a leading 1 see Figure 12 23 For example in order to transmit an 8 bit word the first bit sent is a 1 followed by the 8 bit data word Once the serial port transmits a word in this mode it does not transmit another w...

Page 413: ...pt Sources A serial port has the following interrupt sources Transmit timer interrupt The rising edge of XTSTAT causes a single cycle interrupt pulse to occur When XTINT is 0 this interrupt pulse is disabled Receive timer interrupt The rising edge of RTSTAT causes a single cycle interrupt pulse to occur When RTINT is 0 this interrupt pulse is disabled Transmitter interrupt Occurs immediately follo...

Page 414: ... low All of the serial port operating configurations can be classified in two categories fixed data rate timing and variable data rate timing Both categories support operation in either burst or continuous mode Burst mode operation with variable data rate timing is similar to burst mode operation with fixed data rate timing With variable data rate timing however FSX R and data timing differ slight...

Page 415: ...mately 2 5 CLKX cycles depending on CLKX and H1 frequencies from the time DXR is loaded until FSX occurs With an external FSX the FSX pulse initiates the transfer and the 2 5 cycle delay effectively becomes a setup requirement for loading DXR with respect to FSX In this case you must load DXR no later than three CLKX cycles before FSX occurs Once the XSR is loaded from the DXR an XINT is generated...

Page 416: ...onservative margin of safety in allowing for this delay Once the process begins an XINT and an RINT are generated at the begin ning of each transfer The XINT indicates that the XSR has been loaded from DXR and can be used to cause DXR to be reloaded To maintain continuous transmission in fixed rate mode with frame sync especially with an internally generated FSX DXR must be reloaded early in the o...

Page 417: ...an internal FSX is generated As in the case of continuous operation in fixed data rate mode with frame sync you must reload DXR no later than transmission of the N 3 bit Enabling or Disabling Frame Syncs in Fixed Mode When you use continuous operation in fixed data rate mode you can set and clear R XFSM as desired even during active transfers to enable or disable the use of frame sync pulses as di...

Page 418: ...f transfer With an internally generated FSX see Figure 12 30 transmission is initiated by loading DXR In this mode there is a delay of approximately 3 5 CLKX cycles depending on CLKX and H1 freqency from the time DXR is loaded until FSX occurs With an external FSX the FSX pulse initiates the transfer and the 3 5 cycle delay effectively becomes a setup requirement for loading DXR with respect to FS...

Page 419: ...re 12 31 Variable Standard Mode With Back to Back Frame Syncs DXR Loaded with A XINT Load DSR with B XINT RINT Load DXR with C Read DRR XINT RINT Load DXR with D Read DRR CLKX R FSR FSX External FSX Internal DX DR A1 AN B1 BN C1 C2 R XVAREN 1 R XFSM 0 Continuous operation in variable data rate mode without frame sync see Figure 12 32 is similar to continuous operation without frame sync in fixed d...

Page 420: ...rite a 0 to the serial port global control register The serial ports are halted on RESET 2 Configure the serial port via the serial port global control register with XRESET RRESET 0 and the FSX DX CLKX and FSR DR CLKR port control registers If necessary configure the receive transmit registers timer control with XHLD RHLD 0 timer counter and timer period Refer to section 12 2 14 for more informati...

Page 421: ...e global control register 2 Set the XRESET RRESET and HS bits to 1 in order to start the handshake communication 3 Set the polarity of the serial port pins active high for simplification 4 Although the CLKX CLKR can be set as either input or output set the CLKX as output and the CLKR as input The rest of the bits are user configurable as long as both serial ports have consistent setup You need the...

Page 422: ...pt is disabled S_port timer count 0h S_port timer period 01h Since the data has a leading 1 and the acknowledge signal is a 0 in the hand shake mode the C3x serial port can distinguish between the data and the acknowledge signal Even if the C3x serial port receives the data before the acknowledge signal the data is not misinterpreted as the acknowledge signal and lost Additionally the acknowledge ...

Page 423: ...IMER PERIOD RESET WORD 0H SERIAL PORT TIMER RESET VALUE TEXT START LDP RESET LOAD DATA PAGE POINTER ANDN 10H IE DISABLE SERIAL PORT TRANSMIT INTERRUPT TO CPU SERIAL PORT INITIALIZATION LDI SPORT AR1 LDI RESET R0 LDI 4 IR0 STI R0 AR1 IR0 SERIAL PORT TIMER RESET LDI SPRESET R0 STI R0 AR1 SERIAL PORT RESET LDI SXCTRL R0 SERIAL PORT TX CONTROL REG INITIALIZATON STI R0 AR1 3 LDI STPERIOD R0 SERIAL PORT...

Page 424: ... DX MCLK TMS320C3x TLC320C4x WORD OUT OUT IN IN VCC Analog Out Analog In GND The C3x resets the AIC through the external pin XF0 It also generates the master clock for the AIC through the timer 0 output pin TCLK0 Precise selec tion of a sample rate may require the use of an external oscillator rather than the TCLK0 output to drive the AIC MCLK input In turn the AIC generates the CLKR0 and CLKX0 sh...

Page 425: ...R0 FSR0 CASC XCLK SOUTA SYNC SSF CONV VINA VINB 1 MΩ 12 29 MHz 22 pF 22 pF OSC0 OSC1 C3x TCLK0 The DSP102 A D is interfaced to the C3x serial port receive side the DSP202 D A is interfaced to the transmit side The A Ds and D As are hard wired to run in cascade mode In this mode when the C3x initiates a convert command to the A D via the TCLK0 pin both analog inputs are converted into two 16 bit wo...

Page 426: ... 32 bit word representing the two channels of data to be converted The data transmitted from the C3x DX0 pin is input to both the SINA and SINB inputs of the D A as shown in Example 12 7 The C3x is set up to transfer bits at the maximum rate of about 8 Mbps with a dual channel sample rate of about 44 1 kHz Assuming a 32 MHz CLKIN you can configure this standard mode fixed data rate signaling inter...

Page 427: ...s with auto increment decrement Synchronization of data transfers via external and internal interrupts 12 3 1 DMA Functional Description The DMA controller supports one C30 and C31 or two C32 DMA channels that perform transfers to and from anywhere in the C3x memory map Each DMA channel is controlled by four registers that are mapped in the C3x peripheral address space as shown in Figure 12 35 The...

Page 428: ...t 12 3 1 2 TMS320C32 Two Channel DMA Controller The C32 has an improved DMA that supports two channels and configurable priorities The next sections discuss the new features The C32 has a two channel channel 0 and channel 1 DMA instead of a one channel DMA as in the C30 C31 devices The C32 s DMA functions similarly to that of the C30 C31 DMA but with the addition of DMA CPU priority scheme and int...

Page 429: ... 6 The DMA channel reads a word from the source address register and writes it to a temporary register within the DMA channel 7 After a read by the DMA channel the source address register is increm ented decremented or unchanged depending on the INCSRC or DECSRC bit fields of DMA channel control register 8 After the read operation completes the DMA channel writes the temporary register value to th...

Page 430: ...External or Internal memory 12 3 3 DMA Registers Each DMA channel has four registers designated as follows Control register contains the status and mode information about the associated DMA channel Source address register contains the memory address of data to be read Destination address register contains the memory address where data is written Transfer counter register contains the block size to...

Page 431: ...ÁÁ ÁÁÁÁÁ Á Á ÁÁÁÁÁ ÁÁÁÁÁ 808004h ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ DMA 0 source address Á Á ÁÁÁÁÁ ÁÁÁÁÁ Á Á ÁÁÁÁÁ ÁÁÁÁÁ 808006h ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ DMA 0 destination address Á Á ÁÁÁÁÁ ÁÁÁÁÁ Á Á ÁÁÁÁÁ ÁÁÁÁÁ 808008h ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ DMA 0 transfer counter Á Á ÁÁÁÁÁ ÁÁÁÁÁ Á Á ÁÁÁÁÁ ÁÁÁÁÁ 808010h ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ DMA 1 global control Á Á ÁÁÁÁÁ Á ÁÁÁÁÁ ÁÁÁÁÁ 808014h ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ DMA ...

Page 432: ...egister bits bit names and bit functions Figure 12 36 TMS320C30 and TMS320C31 DMA Global Control Register DECSRC DECDST 31 xx TCINT TC INCDST 15 14 12 11 10 9 8 7 6 5 4 3 2 1 0 INCSRC START R W R W R W R W R W R R W xx R W SYNC STAT R W Notes 1 R read W write 2 xx reserved bit read as 0 Figure 12 37 TMS320C32 DMA0 Global Control Register PRIORITY MODE DMAO PRI DECSRC DECDST 31 TCINT TC INCDST 15 1...

Page 433: ...begun the entire transfer is complete including both read and write operations before stopping If a transfer has not begun none is started 1 1 DMA starts from reset or restarts from the previous state When the DMA completes a transfer the START bits remain in 11 base 2 The DMA starts when the START bits are set to 11 and one of the following conditions applies The transfer counter is set to a valu...

Page 434: ...ion between the events initiating the source and destination transfers The following table summarizes the SYNC bits and DMA synchronization Bit 9 Bit 8 Function 0 0 No synchronization Enabled interrupts are ignored reset value 0 1 Source synchronization A read is per formed when an enabled interrupt occurs 1 0 Destination synchronization A write is per formed when an enabled interrupt occurs 1 1 S...

Page 435: ...n which sets priorities be tween the CPU and DMA channel by alternatingtheir accesses but not exactly equally Priorityrotates between the CPU and DMA accesses when they conflict during consecutive instruction cycles 1 1 DMA has higher priority than the CPU access Ifthe DMA channel and the CPU are requesting the same resource the DMA has priority PRIORITY MODE 0 DMA channels priority mode If PRIORI...

Page 436: ...responding memory access that is the source register for a read and the destination register for a write see Figure 12 39 On system reset 0 is written to these registers Figure 12 39 DMA Controller Address Generation ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ DMA destination address register ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ...

Page 437: ...etch The interrupt is generated after the transfer counter is decremented and after the completion of the write of the last transfer The decrementer checks whether the transfer counter equals 0 after the decre ment is performed As a result if the counter register has a value of 1 then the DMA channel can be halted after only one transfer is performed Thus by set ting the transfer counter to 1 the ...

Page 438: ...A interrupt enable register IE is a 32 bit register located in the CPU register file The CPU interrupt enable bits are in locations 10 1 The DMA interrupt enable bits are in locations 26 16 A 1 in a CPU DMA interrupt enable register bit enables the corresponding interrupt A 0 disables the corresponding interrupt At reset 0 is written to this register Figure 12 41 shows the CPU DMA interrupt enable...

Page 439: ... R W R W R W R W R W R W R W R W R W Notes 1 R read W write 2 xx reserved bit read as 0 Figure 12 42 TMS320C32 CPU DMA Interrupt Enable Register EDINT1 CPU xx xx ETINT0 CPU ETINT1 CPU EDINT0 CPU EINT0 CPU EINT3 DMA1 ETINT1 DMA1 EXINT0 DMA0 EINT1 DMA0 EINT2 DMA1 ETINT1 DMA0 EDINT1 DMA0 ETINT0 DMA1 ERINT0 DMA1 EINT3 DMA0 EINT2 DMA0 EINT0 DMA0 EINT1 DMA1 EINT0 DMA1 EDINT0 DMA1 31 30 29 28 27 26 25 24...

Page 440: ... only EDINT1 CPU 0 CPU DMA1 controller interrupt enable C32 only EINT0 DMA 0 DMA external interrupt 0 enable C30 and C31 only EINT1 DMA 0 DMA external interrupt 1 enable C30 and C31 only EINT2 DMA 0 DMA external interrupt 2 enable C30 and C31 only EINT3 DMA 0 DMA external interrupt 3 enable C30 and C31 only EINT0 DMA0 0 DMA0 external interrupt 0 enable C32 only EINT1 DMA0 0 DMA0 external interrupt...

Page 441: ...le C32 only EINT2 DMA1 0 DMA1 external interrupt 2 enable C32 only EINT3 DMA1 0 DMA1 external interrupt 2 enable C32 only 12 3 5 TMS320C32 DMA Internal Priority Schemes Because all accesses made by the two DMA channels take place over one common internal DMA data and address bus a priority scheme for bus arbitra tion is required Within the DMA controller two priority schemes are used to designate ...

Page 442: ...ses Arbitration is neces sary only when a resource conflict exists between the DMA controller and the CPU The arbitration causes no delay When there is no conflict the CPU and DMA controller accesses proceed in parallel All arbitration between the CPU and the DMA controller is on an access basis DMA controller internal memory access starts during H3 see Section 8 5 Clocking Memory Access for more ...

Page 443: ...ion cycles When there is no conflict in a previous instruction cycle the CPU has priority 1 0 Reserved 1 1 DMA access is higher priority than the CPU access If the DMA channel and the CPU request the same resource the DMA has priority 12 3 7 DMA and Interrupts The DMA controller uses interrupts in the following way It can send interrupts to the CPU or other DMA channel when a block transfer finish...

Page 444: ...hannels This section describes the following four synchronization mechanisms No synchronization SYNC 0 0 When SYNC 0 0 no synchronization is performed The DMA performs reads and writes whenever there are no conflicts All interrupts are ignored and are considered to be globally disabled However no bits in the DMA interrupt enable register are changed Figure 12 43 shows the synchro nization mechanis...

Page 445: ...d until the read is complete Though the DMA interrupts are considered globally disabled no bits in the DMA interrupt enable regis ter are changed A write is not performed until an interrupt is received by the DMA while the read is performed without waiting for the interrupt Figure 12 45 shows the synchronization mechanism when SYNC 1 0 Figure 12 45 Mechanism for DMA Destination Synchronization Sta...

Page 446: ...s a read DMA channel performs a write Go to start Idle until enabled interrupt is received Enable DMA interrupts globally Idle until enabled interrupt is received Disable DMA interrupts globally Enable DMA interrupts globally Clear corresponding IF bit Clear corresponding IF bit 12 3 8 DMA Memory Transfer Timing The C30 and C31 devices provide one DMA channel while the C32 device provides two DMA ...

Page 447: ...p you calculate the transfer timing for certain DMA setups For simplification the following section focuses on a single channel DMA memory transfer timing with no conflict with the CPU or other DMA channels You can obtain the actual DMA transfer timing by combining the calculations for single channel DMA transfer timing with those for bus resource conflict situations 12 3 8 1 Single DMA Memory Tra...

Page 448: ...0 STRB1 MSTRB bus R1 R1 R1 I R2 R2 R2 I R3 R3 R3 I Source STRB STRB0 STRB1 MSTRB bus Cr Cr Cr 2 Cr 1 T Destination on chip W1 W2 W3 Source IOSTRB bus R1 R1 R1 R1 I R2 R2 R2 R2 I R3 R3 R3 R3 I Source IOSTRB bus Cr Cr Cr 3 Cr 1 T Destination on chip W1 W2 W3 Legend T Number of transfers W Single cycle writes Cr Source read wait states Rn Multicycle reads Cw Destination write wait states Wn Multicycl...

Page 449: ...2 Cr 2 Cw T 0 5 T 1 Destination STRB W1 W1 W1 W1 W2 W2 W2 W2 STRB STRB0 STRB1 bus Cw Cw 3 5 Cr 2 Cw T 5 T 1 C30 only Source R1 R1 R1 R1 I R2 R2 R2 R2 I R3 R3 R3 R3 I R4 R4 R4 R4 Source IOSTRB Cr Cr Cr Cr 3 Cr 2 Cw 2 Cw max 1 Cr Cw 1 T 1 Destination W1 W1 W1 W1 W2 W2 W2 W2 W3 W3 W3 W3 T 1 STRB bus Cw Cw Cw Legend T Number of transfers W Single cycle writes Cr Source read wait states Rn Multicycle r...

Page 450: ...us W1 W1 W1 W1 W2 W2 W2 W2 3 Cr 2 Cw T 0 5 T 1 Cw Cw C30 only Source STRB bus R1 R1 R1 I R2 R2 R2 I R3 R3 R3 I Cr Cr Cr 2 Cr 2 Cw 2 Cw max 1 Cr Cw 1 Destination MSTRB bus W1 W1 W1 W1 W2 W2 W2 W2 W3 W3 W3 W3 T 1 Cw Cw Cw Legend T Number of transfers W Single cycle writes Cr Source read wait states Rn Multicycle reads Cw Destination write wait states Wn Multicycle writes R Single cycle reads I Inter...

Page 451: ...R3 I Cr Cr Cr 2 Cr 2 Cw 2 Cw max 1 Cr Cw 1 T 1 Destination IOSTRB bus W1 W1 W1 W1 W2 W2 W2 W2 W3 W3 W3 W3 max 1 Cr Cw 1 T 1 Destination IOSTRB bus Cw Cw Cw Source STRB0 STRB1 MSTRB bus R1 R1 R1 I R2 R2 R2 I Cr Cr 2 C 2 C T T 1 Destination IOSTRB W1 W1 W1 W1 W2 W2 W2 W2 2 Cr 2 Cw T T 1 Cw Cw Legend T Number of transfers W Single cycle writes Cr Source read wait states Rn Multicycle reads Cw Destina...

Page 452: ...atched interrupt that may no longer exist In the event of a CPU DMA access conflict the CPU always prevails Care fully allocate the different sections of the program in memory for faster execution If a CPU program access conflicts with a DMA access enabling the cache helps if the program is located in external memory DMA on chip access happens during the H3 phase Note Expansion and Peripheral Buse...

Page 453: ... for the DMA When linking the examples you should allocate section memory addresses carefully to avoid CPU DMA conflict In the C3x the CPU always prevails in cases of conflict In the event of a CPU program DMA data conflict cache enabling helps if the text section is in external memory For example when linking the code in Example 12 8 Example 12 9 and Example 12 10 the text section can be allocate...

Page 454: ... DESTIN R0 INITIALIZE DMA DESTINATION ADDRESS REGISTER STI R0 AR0 6 LDI COUNT R0 INITIALIZE DMA TRANSFER COUNTER REGISTER STI R0 AR0 8 OR 400H IE ENABLE INTERRUPT FROM DMA TO CPU OR 2000H ST ENABLE CPU INTERRUPTS GLOBALLY LDI CONTROL R0 INITIALIZE DMA GLOBAL CONTROL REGISTER STI R0 AR0 START DMA TRANSFER BU END Example 12 9 sets up the DMA to transfer data 128 words from the serial port 0 input re...

Page 455: ...ERIOD WORD 00020000H SERIAL PORT TIMER PERIOD SPRESET WORD 01300080H SERIAL PORT RESET RESET WORD 0H SERIAL PORT TIMER RESET TEXT START LDP DMA LOAD DATA PAGE POINTER DMA INITIALIZATION LDI DMA AR0 POINT TO DMA GLOBAL CONTROL REGISTER LDI SPORT AR1 LDI RESET R0 STI R0 AR1 4 RESET SPORT TIMER LDI RESET1 R0 STI R0 AR0 RESET DMA LDI SPRESET R0 STI R0 AR1 RESET SPORT LDI SOURCE R0 INITIALIZE DMA SOURC...

Page 456: ...bit of data to the shifter an initial CPU write to the serial port is required to trigger XINT0 to enable the first DMA transfer Example 12 10 DMA Transfer With Serial Port Transmit Interrupt TITLE DMA TRANSFER WITH SERIAL PORT TRANSMIT INTERRUPT GLOBAL START DATA DMA WORD 808000H DMA GLOBAL CONTROL REG ADDRESS CONTROL WORD 0E13H DMA GLOBAL CONTROL REG INITIALIZATION SOURCE WORD _ARRAY 1 DATA SOUR...

Page 457: ...L CONTROL REGISTER STI R0 AR0 START DMA TRANSFER SERIAL PORT INITIALIZATION LDI SXCTRL R0 SERIAL PORT TX CONTROL REG INITIALIZATION STI R0 AR1 2 LDI STPERIOD R0 SERIAL PORT TIMER PERIOD INITIALIZATION STI R0 AR1 6 LDI STCTRL R0 SERIAL PORT TIMER CONTROL REG INITIALIZATION STI R0 AR1 4 LDI SGCCTRL R0 SERIAL PORT GLOBAL CONTROL REG INITIALIZATION STI R0 AR1 CPU WRITES THE FIRST WORD TRIGGERING EVENT...

Page 458: ...DMA destination address 809C00h DMA transfer counter 000000C8h DMA global control 00000D43h CPU DMA interrupt enable IE 00200400h Transfer a 200 word block of data from off chip memory to the serial port 0 transmit register and generate an interrupt on completion Synchronize with the serial port 0 transmit interrupt DMA source address 809C00h DMA destination address 808048h DMA transfer counter 00...

Page 459: ...al syntax forms to simplify the assembly language for special case instructions These optional forms are listed and explained Each of the individual instructions is described and listed in alphabetical order see subsection 13 6 2 Optional Assembler Syntax on page 13 34 Example instructions demonstrate the special format and explain its content This chapter discusses these topics Topic Page 13 1 In...

Page 460: ...he C3x supports 13 load and store instructions see Table 13 1 These instructions can Load a word from memory into a register Store a word from a register into memory Manipulate data on the system stack Two of these instructions can load data conditionally This is useful for locating the maximum or minimum value in a data set See Section 13 5 on page 13 28 for detailed information on condition code...

Page 461: ...OR Bitwise logical OR ADDF Add floating point values RND Round floating point value ADDI Add integers ROL Rotate left AND Bitwise logical AND ROLC Rotate left through carry ANDN Bitwise logical AND with complement ROR Rotate right ASH Arithmetic shift RORC Rotate right through carry CMPF Compare floating point values SUBB Subtract integers with borrow CMPI Compare integers SUBC Subtract integers c...

Page 462: ...3 Add floating point values MPYI3 Multiply integers ADDI3 Add integers OR3 Bitwise logical OR AND3 Bitwise logical AND SUBB3 Subtract integers with borrow ANDN3 Bitwise logical AND with complement SUBF3 Subtract floating point values ASH3 Arithmetic shift SUBI3 Subtract integers CMPF3 Compare floating point values TSTB3 Test bit fields CMPI3 Compare integers XOR3 Bitwise exclusive OR LSH3 Logical ...

Page 463: ...ow power control instruction group consists of three instructions that affect the low power modes The low power idle IDLE2 instruction allows extremely low power mode The divide clock by 16 LOPOWER instruction reduces the rate of the input clock frequency The restore clock to regular speed MAXSPEED instruction causes the resumption of full speed operation Table 13 5 lists the low power control ins...

Page 464: ...rithmetic operations Arithmetic logical instructions used in parallel with a store instruction Each instruction in a pair is entered as a separate source statement The second instruction in the pair must be preceded by two vertical bars Table 13 7 lists the valid instruction pairs Table 13 7 Parallel Instructions a Parallel arithmetic with store instructions Mnemonic Description ABSF STF Absolute ...

Page 465: ... shift and store integer MPYF3 STF Multiply floating point values and store floating point value MPYI3 STI Multiply integer and store integer NEGF STF Negate floating point value and store floating point value NEGI STI Negate integer and store integer NOT STI Complement value and store integer OR3 STI Bitwise logical OR value and store integer STF STF Store floating point values STI STI Store inte...

Page 466: ...integer These parallel instructions have been enhanced on the following devices C31 silicon revision 6 0 or greater C32 silicon revision 2 0 or greater These devices support greater combinations of operands by also allowing the use of any CPU register whenever an indirect operand is required The particular instruction description details the operand combination To support these new modes you need ...

Page 467: ... mechanism Fetching an illegal undefined opcode can cause the execution of an undefined operation Proper use of the TI TMS320 floating point software tools will not generate an illegal opcode Only the following conditions can cause the generation of an illegal opcode Misuse of the tools An error in the ROM code Defective RAM ...

Page 468: ...DN Bitwise logical AND with complement Dreg AND src Dreg ANDN3 Bitwise logical ANDN 3 operand src1 AND src2 Dreg ASH Arithmetic shift If count 0 Shifted Dreg left by count Dreg Else Shifted Dreg right by count Dreg ASH3 Arithmetic shift 3 operand If count 0 Shifted src left by count Dreg Else Shifted src right by count Dreg Legend ARn auxiliary register n AR7 AR0 RE repeat interrupt register C car...

Page 469: ... 1 PC CMPF Compare floating point values Set flags on Rn src CMPF3 Compare floating point values 3 operand Set flags on src1 src2 CMPI Compare integers Set flags on Dreg src CMPI3 Compare integers 3 operand Set flags on src1 src2 Legend ARn auxiliary register n AR7 AR0 RE repeat interrupt register C carry bit RM repeat mode bit Csrc conditional branch addressing modes Rn register address R7 R0 cou...

Page 470: ...opping internal clocks LDE Load floating point exponent src exponent Rn exponent LDF Load floating point value src Rn LDFcond Load floating point value conditionally If cond true src Rn Else Rn is not changed LDFI Load floating point value interlocked Signal interlocked operation src Rn LDI Load integer src Dreg Legend ARn auxiliary register n AR7 AR0 RE repeat interrupt register C carry bit RM re...

Page 471: ...loating point values src Rn Rn MPYF3 Multiply floating point value 3 operand src1 src2 Rn MPYI Multiply integers src Dreg Dreg MPYI3 Multiply integers 3 operand src1 src2 Dreg NEGB Negate integer with borrow 0 src C Dreg NEGF Negate floating point value 0 src Rn NEGI Negate integer 0 src Dreg Legend ARn auxiliary register n AR7 AR0 RE repeat interrupt register C carry bit RM repeat mode bit Csrc c...

Page 472: ...und floating point value Round src Rn ROL Rotate left Dreg rotated left 1 bit Dreg ROLC Rotate left through carry Dreg rotated left 1 bit through carry Dreg ROR Rotate right Dreg rotated right 1 bit Dreg RORC Rotate right through carry Dreg rotated right 1 bit through carry Dreg Legend ARn auxiliary register n AR7 AR0 RE repeat interrupt register C carry bit RM repeat mode bit Csrc conditional bra...

Page 473: ...ubtract integers with borrow 3 operand src1 src2 C Dreg SUBC Subtract integers conditionally If Dreg src 0 Dreg src 1 OR 1 Dreg Else Dreg 1 Dreg SUBF Subtract floating point values Rn src Rn SUBF3 Subtract floating point values 3 operand src1 src2 Rn Legend ARn auxiliary register n AR7 AR0 RE repeat interrupt register C carry bit RM repeat mode bit Csrc conditional branch addressing modes Rn regis...

Page 474: ...B3 Test bit fields 3 operand src1 AND src2 XOR Bitwise exclusive OR Dreg XOR src Dreg XOR3 Bitwise exclusive OR 3 operand src1 XOR src2 Dreg Legend ARn auxiliary register n AR7 AR0 RE repeat interrupt register C carry bit RM repeat mode bit Csrc conditional branch addressing modes Rn register address R7 R0 count shift value general addressing modes RS repeat start register cond condition code SP s...

Page 475: ... src3 dst2 ADDF3 STF Add floating point value src1 src2 dst1 src3 dst2 ADDI3 STI Add integer src1 src2 dst1 src3 dst2 AND3 STI Bitwise logical AND src1 AND src2 dst1 src3 dst2 ASH3 STI Arithmetic shift If count 0 src2 count dst1 src3 dst2 Else src2 count dst1 src3 dst2 FIX STI Convert floating point value to integer Fix src2 dst1 src3 dst2 FLOAT STF Convert integer to floating point value Float sr...

Page 476: ...1 src3 dst2 NEGF STF Negate floating point value 0 src2 dst1 src3 dst2 NEGI STI Negate integer 0 src2 dst1 src3 dst2 NOT STI Complement src1 dst1 src3 dst2 OR3 STI Bitwise logical OR src1 OR src2 dst1 src3 dst2 STF STF Store floating point value src1 dst1 src3 dst2 STI STI Store integer src1 dst1 src3 dst2 Legend count register addr R7 R0 op3 register addr R0 or R1 dst1 register addr R7 R0 op6 reg...

Page 477: ...t2 c Parallel multiply and add subtract instructions Mnemonic Description Operation MPYF3 ADDF3 Multiply and add floating point value op1 x op2 op3 op4 op5 op6 MPYF3 SUBF3 Multiply and subtract floating point value op1 x op2 op3 op4 op5 op6 MPYI3 ADDI3 Multiply and add integer op1 x op2 op3 op4 op5 op6 MPYI3 SUBI3 Multiply and subtract integer op1 x op2 op3 op4 op5 op6 Legend count register addr R...

Page 478: ...x the destination operand is signified by dst and the source operand by src operation defines an operation to be performed on the operands using the general addressing modes Bits 31 29 are 0 indicating general addressing mode instructions Bits 22 and 21 specify the general addressing mode G field which defines how bits 15 0 are to be interpreted for addressing the src operand Options for bits 22 a...

Page 479: ...dification field that goes with the ARn field Refer to Table 13 10 on page 13 22 for further information Figure 13 1 Encoding for General Addressing Modes G Destination Source Operands 31 29 28 23 22 21 20 16 15 11 10 8 7 5 4 0 0 0 0 operation 0 0 dst 0 0 0 0 0 0 0 0 0 0 0 src 0 0 0 operation 0 1 dst direct 0 0 0 operation 1 0 dst modn ARn disp 0 0 0 operation 1 1 dst immediate ...

Page 480: ...With postdisplacement subtract and circular modify b Indirect addressing with index register IR0 Mod Field Syntax Operation Description 01000 ARn IR0 addr ARn IR0 With preindex IR0 add 01001 ARn IR0 addr ARn IR0 With preindex IR0 subtract 01010 ARn IR0 addr ARn IR0 ARn ARn IR0 With preindex IR0 add and modify 01011 ARn IR0 addr ARn IR0 ARn ARn IR0 With preindex IR0 subtract and modify 01100 ARn IR...

Page 481: ... modify 10101 ARn IR1 addr ARn ARn ARn IR1 With postindex IR1 subtract and modify 10110 ARn IR1 addr ARn ARn circ ARn IR1 With postindex IR1 add and circular modify 10111 ARn IR1 addr ARn ARn circ ARn IR1 With postindex IR1 subtract and circular modify d Indirect addressing special cases Mod Field Syntax Operation Description 11000 ARn addr ARn Indirect 11001 ARn IR0 B addr ARn ARn B ARn IR0 With ...

Page 482: ... 0 are to be interpreted for addressing the SRC operands Bits 15 8 define the SRC1 address bits 7 0 define the SRC2 address Options for bits 22 and 21 T are as follows T src1 addressing modes src2 addressing modes 0 0 Register mode any CPU register Register mode any CPU register 0 1 Indirect mode disp 0 1 IR0 IR1 Register mode any CPU register 1 0 Register mode any CPU register Indirect mode disp ...

Page 483: ...hat use parallel addressing indicated by two vertical bars allow the most parallelism possible The destination operands are indicated as d1 and d2 signifying dst1 and dst2 respectively see Figure 13 3 The source operands signified by src1 and src2 use the extended precision registers Operation refers to the parallel operation to be performed Figure 13 3 Encoding for Parallel Addressing Modes 31 30...

Page 484: ... of 1 is implied and is not explicitly coded in the instruction word In the encoding shown for this mode in Figure 13 3 if the src3 and src4 fields use the same auxiliary register both addresses are correctly generated but only the value created by the src3 field is saved in the auxiliary register specified The assembler issues a warning if you specify this condition The encoding of these parallel...

Page 485: ...ch D 0 for a standard branch or D 1 for a delayed branch The condition field cond specifies the condition checked to determine what action to take that is whether to branch see Table 13 12 on page 13 30 for a list of condition codes Figure 13 5 shows the encoding for conditional branch addressing Figure 13 5 Encoding for Conditional Branch Addressing Modes a DBcond D 31 26 25 24 22 21 20 16 15 5 4...

Page 486: ... the condition flags according to the contents of any of the CPU registers The condition flags are modified by most instructions when either of the pre ceding conditions is established and either of the following two cases occurs A result is generated when the specified operation is performed to infinite precision This is appropriate for compare and test instructions that do not store results in a...

Page 487: ... not occur N Negative condition flag Logical operations assign N the state of the MSB of the output value For logical operations V is set to the state of the MSB For integer and floating point operations N is set if the result is negative and cleared otherwise A 0 is positive Z Zero condition flag For logical integer and floating point operations Z is set if the output is 0 and cleared otherwise V...

Page 488: ...gned compares Condition Code Description Flag LO LS HI HS EQ NE 00001 00010 00011 00100 00101 00110 Lower than Lower than or same as Higher than Higher than or same as Equal to Not equal to C C OR Z C AND Z C Z Z c Signed compares Condition Code Description Flag LT LE GT GE EQ NE 00111 01000 01001 01010 00101 00110 Less than Less than or equal to Greater than Greater than or equal to Equal to Not ...

Page 489: ...flags Condition Code Description Flag NN N NZ Z NV V NUF UF NC C NLV LV NLUF LUF ZUF 01010 00111 00110 00101 01100 01101 01110 01111 00100 00001 10000 10001 10010 10011 10100 Non negative Negative Nonzero Zero No overflow Overflow No underflow Underflow No carry Carry No latched overflow Latched overflow No latched floating point underflow Latched floating point underflow Zero or floating point un...

Page 490: ...dividual instruction description section Also an example instruction shows the special format used and explains its content A functional grouping of the instructions as well as a complete instruction set summary can be found in Section 13 1 on page 13 2 Appendix A lists the opcodes for all of the instructions Refer to Chapter 6 for information on memory addressing Code examples using many of the i...

Page 491: ... to destination y Mantissa field sign fraction of x Exponent field of x op1 op2 Operation 1 performed in parallel with operation 2 x AND y x OR y x XOR y x Bitwise logical AND of x and y Bitwise logical OR of x and y Bitwise logical XOR of x and y Bitwise logical complement of x x y x y SP SP Shift x to the left y bits Shift x to the right y bits Increment SP and use incremented SP as address Use ...

Page 492: ...f the pertinent parallel instructions You can write all 3 operand comparison instructions without the 3 For example CMPI3 R0 AR0 can be written as CMPI R0 AR0 Instructions affected CMPI3 CMPF3 TSTB3 Indirect operands with an explicit 0 displacement are allowed In 3 operand or parallel instructions operands with 0 displacement are automatically converted to no displacement mode For example LDI AR0 ...

Page 493: ...the parallel bars indicating part 2 of a parallel instruction anywhere on the line from column 0 to the mnemonic For example ADDI can be written as ADDI STI STI If the second operand of a parallel instruction is the same as the third desti nation register operand you can omit the third operand This allows you to write 3 operand parallel instructions that look like normal 2 operand instruc tions Fo...

Page 494: ...ster Extended precision register Extended precision register Extended precision register Extended precision register AR0 AR1 AR2 AR3 AR4 AR5 AR6 AR7 R8 R9 R10 R11 R12 R13 R14 R15 Auxiliary register Auxiliary register Auxiliary register Auxiliary register Auxiliary register Auxiliary register Auxiliary register Auxiliary register DP IR0 IR1 BK SP R16 R17 R18 R19 R20 Data page pointer Index register...

Page 495: ... 6 3 Individual Instruction Descriptions Each assembly language instruction for the C3x is described in this section in alphabetical order The description includes the assembler syntax operation operands encoding description cycles status bits mode bit and examples ...

Page 496: ...econd line The first instruction in the pair can have a label but the second instruction cannot have a label Operation src dst or src2 dst1 src3 dst2 The instruction operation sequence describes the processing that occurs when the instruction is executed For parallel instructions the operation sequence is performed in parallel Conditional effects of status register specified modes are listed for s...

Page 497: ... if an integer or floating point overflow occurs unchanged otherwise UF Floating point underflow condition flag 1 if a floating point underflow occurs 0 otherwise N Negative condition flag 1 if a negative result is generated 0 other wise In some instructions this flag is the MSB of the output Z Zero condition flag 1 if a 0 result is generated 0 otherwise For logical and shift instructions 1 if a 0...

Page 498: ...ve format shows the effect of the code on system pointers for example DP or SP registers for example R1 or R5 memory at specific locations and the seven status bits The values given for the registers include the leading 0s to show the exponent in floating point operations Decimal conversions are provided for all register and memory locations The seven status bits are listed in the order in which t...

Page 499: ...s if src man 80000000h and src exp 7Fh The result is dst man 7FFFFFFFh and dst exp 7Fh Cycles 1 Status Bits These condition flags are modified only if the destination register is R7 R0 LUF Unaffected LV 1 if a floating point overflow occurs unchanged otherwise UF 0 N 0 Z 1 if a 0 result is generated 0 otherwise V 1 if a floating point overflow occurs 0 otherwise C Unaffected Mode Bit OVM Operation...

Page 500: ... point store are performed in paral lel All registers are read at the beginning and loaded at the end of the execute cycle If one of the parallel operations STF reads from a register and the opera tion being performed in parallel ABSF writes to the same register STF accepts the contents of the register as input before it is modified by the ABSF If src2 and dst2 point to the same location src2 is r...

Page 501: ...33C0 0000 R4 05 74C0 0000 AR3 80 9800 AR3 8098AF AR7 80 98C5 AR7 8098C5 IR1 0AF IR1 0AF LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data Memory 8098AF 58B4000 8098AF 58B4000 8098C4 0 8098C4 733C000 1 79750e 02 6 118750e 01 6 118750e 01 6 118750e 01 1 79750e 02 Note Cycle Count See Section 8 5 2 Data Loads and Stores on page 8 24 for the effects of operand ordering on the cycle ...

Page 502: ...d into the dst register The src and dst operands are assumed to be signed integers An overflow occurs if src 80000000h If ST OVM 1 the result is dst 7FFFFFFFh If ST OVM 0 the result is dst 80000000h Cycles 1 Status Bits These condition flags are modified only if the destination register is R7 R0 LUF Unaffected LV 1 if an integer overflow occurs unchanged otherwise UF 0 N 0 Z 1 if a 0 result is gen...

Page 503: ... Example 1 ABSI R0 R0 or ABSI R0 Before Instruction After Instruction R0 00 FFFF FFCB R0 00 0000 0035 53 53 Example 2 ABSI AR1 R3 Before Instruction After Instruction R3 00 0000 0000 R3 00 0000 0035 AR1 00 0020 AR1 00 0020 Data memory 20 0FFFFFFCB 20 0FFFFFFCB 53 53 53 ...

Page 504: ... disp 0 1 IR0 IR1 Opcode 31 24 23 16 8 7 0 15 1 1 0 0 1 0 dst1 src2 dst2 1 src3 0 0 0 Description An integer absolute value and an integer store are performed in parallel All registers are read at the beginning and loaded at the end of the execute cycle If one of the parallel operations STI reads from a register and the operation being performed in parallel ABSI writes to the same register STI acc...

Page 505: ...fected Mode Bit OVM Operation is affected by OVM bit value Example ABSI AR5 1 R5 STI R1 AR2 IR1 Before Instruction After Instruction R1 00 0000 0042 R1 00 0000 0042 R5 00 0000 0000 R5 00 0000 0035 AR2 80 98FF AR2 80 98F0 AR5 80 99E2 AR5 80 99E2 IR1 0F IR1 0F LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 8098FF 2 8098FF 42 8099E1 0FFFFFFCB 8099E1 0FFFFFFCB 66 53 2 66 5...

Page 506: ...d integers Cycles 1 Status Bits These condition flags are modified only if the destination register is R7 R0 LUF Unaffected LV 1 if an integer overflow occurs unchanged otherwise UF 0 N 1 if a negative result is generated 0 otherwise Z 1 if a 0 result is generated 0 otherwise V 1 if an integer overflow occurs 0 otherwise C 1 if a carry occurs 0 otherwise OVM Operation is affected by OVM bit value ...

Page 507: ...ter Opcode 31 2423 16 8 7 0 15 0 0 1 0 0 0 T src1 0 dst 0 src2 0 Description The sum of the src1 and src2 operands and the carry C flag is loaded into the dst register The src1 src2 and dst operands are assumed to be signed integers Cycles 1 Status Bits These condition flags are modified only if the destination register is R7 R0 LUF Unaffected LV 1 if an integer overflow occurs unchanged otherwise...

Page 508: ... 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 1 C 1 Data memory 809908 0FFFFFFCB 809908 0FFFFFFCB 53 102 53 102 50 Example 2 ADDC3 R2 R7 R0 Before Instruction After Instruction R0 00 0000 0000 R0 00 0000 123F R2 00 0000 02BC R2 00 0000 02BC R7 00 0000 0F82 R7 00 0000 0F82 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 1 C 0 700 700 3970 3970 4671 Note Cycle Count See Section 8 5 2 Data Loads and Stores ...

Page 509: ...he dst register The dst and src operands are assumed to be floating point numbers Cycles 1 Status Bits These condition flags are modified only if the destination register is R7 R0 LUF 1 if a floating point underflow occurs unchanged otherwise LV 1 if a floating point overflow occurs unchanged otherwise UF 1 if a floating point underflow occurs 0 otherwise N 1 if a negative result is generated 0 ot...

Page 510: ...fore Instruction After Instruction R5 05 7980 0000 R5 09 052C 0000 AR 4809800 AR4 80992B IR 112B IR1 12B LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 86B2800 86B2800 5 3268750e 02 4 7031250e 02 4 7013250e 02 6 23750e 01 809800 809800 ...

Page 511: ... 0 0 1 T src2 src1 0 dst 0 0 Description The sum of the src1 and src2 operands is loaded into the dst register The src1 src2 and dst operands are assumed to be floating point numbers Cycles 1 Status Bits These condition flags are modified only if the destination register is R7 R0 LUF 1 if a floating point underflow occurs unchanged otherwise LV 1 if a floating point overflow occurs unchanged other...

Page 512: ... 02 6 23750e 01 4 7031250e 02 Example 2 ADDF3 AR1 1 AR7 IR0 R4 Before Instruction After Instruction R4 00 0000 0000 R4 07 0DB2 0000 AR1 80 9820 AR1 80 9820 AR7 80 99FO AR7 80 99F8 IR0 8 IR0 8 LUF 0 LUF 0 LV 0 LV 0 UF 0 UV 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 809821h 700F000 809821h 700F000 8099F0h 34C2000 8099F0h 34C2000 1 28940e 02 1 27590e 01 1 41695313e 02 1 28940e 02 1 27590e 01 Note ...

Page 513: ...int addition and a floating point store are performed in parallel All registers are read at the beginning and loaded at the end of the execute cycle If one of the parallel operations STF reads from a register and the operation being performed in parallel ADDF3 writes to the same register STF accepts as input the contents of the register before it is modified by the ADDF3 If src2 and dst2 point to ...

Page 514: ...R5 08 2020 0000 AR2 80 98F3 AR2 80 98F3 AR3 80 9800 AR3 80 9800 IR1 0A5 IR1 0A5 LUF 0 LUF 0 LV 0 LV 0 UF 0 UV 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 8098A5h 733C000 8098A5h 733C000 8098F3h 0 8098F3h 57B4000 1 4050e 02 6 281250e 01 1 79750e 02 1 4050e 02 6 281250e 01 3 20250e 02 1 79750e 02 6 28125e 01 Note Cycle Count See Section 8 5 2 Data Loads and Stores on page 8 24 for the effects of o...

Page 515: ...umed to be signed integers Cycles 1 Status Bits These condition flags are modified only if the destination register is R7 R0 LUF Unaffected LV 1 if an integer overflow occurs unchanged otherwise UF 0 N 1 if a negative result is generated 0 otherwise Z 1 if a 0 result is generated 0 otherwise V 1 if an integer overflow occurs 0 otherwise C 1 if a carry occurs 0 otherwise OVM Operation is affected b...

Page 516: ... 24 23 16 8 7 0 15 0 0 1 0 0 0 0 T src2 dst src1 1 0 Description The sum of the src1 and src2 operands is loaded into the dst register The src1 src2 and dst operands are assumed to be signed integers Cycles 1 Status Bits These condition flags are modified only if the destination register is R7 R0 LUF Unaffected LV 1 if an integer overflow occurs unchanged otherwise UF 0 N 1 if a negative result is...

Page 517: ...C 0 C 0 220 220 16 160 380 160 Example 2 ADDI3 AR3 1 AR6 IR0 R2 Before Instruction After Instruction R2 00 0000 0010 R2 00 0000 6598 AR3 80 9802 AR3 80 9802 AR6 80 9930 AR6 80 9918 IR0 18 IR0 18 LUF 0 LUF 0 LV 0 LV 0 UF 0 UV 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 809801 2AF8 809801 2AF8 809930 3A98 809930 3A98 16 11 000 15 000 26 000 11 000 15 000 Note Cycle Count See Section 8 5 2 Data Loa...

Page 518: ...c3 dst2 Description An integer addition and an integer store are performed in parallel All registers are read at the beginning and loaded at the end of the execute cycle If one of the parallel operations STI reads from a register and the operation being performed in parallel ADDI3 writes to the same register STI accepts the con tents of the register as input before it is modified by the ADDI3 If s...

Page 519: ...000 0208 R3 00 0000 0035 R3 00 0000 0035 R5 00 0000 00DC R5 00 0000 00DC AR0 80 992C AR0 80 9920 AR7 80 983B AR7 80 983B IR0 OC IR0 OC LUF 0 LUF 0 LV 0 LV 0 UF 0 UV 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 80992C 12C 80992C 12C 80983B 0 80983B 35 53 300 300 53 220 220 53 520 Note Cycle Count See Section 8 5 2 Data Loads and Stores on page 8 24 for the effects of operand ordering on the cycle ...

Page 520: ...erands is loaded into the dst register The dst and src operands are assumed to be unsigned integers Cycles 1 Status Bits These condition flags are modified only if the destination register is R7 R0 LUF Unaffected LV Unaffected UF 0 N MSB of the output Z 1 if a 0 result is generated 0 otherwise V 0 C Unaffected OVM Operation is not affected by OVM bit value Example AND R1 R2 Before Instruction Afte...

Page 521: ...ect disp 0 1 IR0 IR1 1 1 indirect disp 0 1 IR0 IR1 Opcode 31 24 23 16 8 7 0 15 0 0 1 0 0 0 0 dst src1 src2 1 1 T Description The bitwise logical AND between the src1 and src2 operands is loaded into the destination register The src1 src2 and dst operands are assumed to be unsigned integers Cycles 1 Status Bits These condition flags are modified only if the destination register is R7 R0 LUF Unaffec...

Page 522: ... V 0 V 0 C 0 C 0 Data memory 8098F4h 30 8098F4h 30 809952h 123 809952h 123 Example 2 AND3 AR5 R7 R4 Before Instruction After Instruction R4 00 0000 0000 R4 00 0000 0002 R7 00 0000 0002 R7 00 0000 0002 AR5 80 985C AR5 80 985C LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 80985Bh 0AFF 80985Bh 0AFF Note Cycle Count See Section 8 5 2 Data Loads and Stores on page 8 24 for...

Page 523: ...direct disp 0 1 IR0 IR1 Opcode 31 24 23 16 8 7 0 15 1 1 0 1 0 0 0 dst1 src1 src3 dst2 src2 Description A bitwise logical AND and an integer store are performed in parallel All regis ters are read at the beginning and loaded at the end of the execute cycle If one of the parallel operations STI reads from a register and the operation be ing performed in parallel AND3 writes to the same register STI ...

Page 524: ...00 0035 R3 00 0000 0035 R4 00 0000 A323 R4 00 0000 A323 R7 00 0000 0000 R7 00 0000 0003 AR1 80 99F1 AR1 80 99F1 AR2 80 983F AR2 80 983F LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 8099F9h 5C53 8099F9h 5C53 80983Fh 0 80983Fh 35 53 53 53 Note Cycle Count See Section 8 5 2 Data Loads and Stores on page 8 24 for the effects of operand ordering on the cycle count Mode Bi...

Page 525: ... 15 0 0 0 0 0 0 1 dst src 1 0 G Description The bitwise logical AND between the dst operand and the bitwise logical com plement of the src operand is loaded into the dst register The dst and src operands are assumed to be unsigned integers Cycles 1 Status Bits These condition flags are modified only if the destination register is R7 R0 LUF Unaffected LV Unaffected UF 0 N MSB of the output Z 1 if a...

Page 526: ...ith Complement 13 68 Example ANDN 980Ch R2 Before Instruction After Instruction R2 00 0000 0C2F R2 00 0000 042D DP 080 DP 080 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 80980Ch 0A02 80980Ch 0A02 ...

Page 527: ...rect disp 0 1 IO0 IR1 dst register Rn 0 n 27 Opcode 31 24 23 16 8 7 0 15 0 0 1 0 0 0 1 dst src1 0 0 T src2 Description The bitwise logical AND between the src1 operand and the bitwise logical complement of the src2 operand is loaded into the dst register The src1 src2 and dst operands are assumed to be unsigned integers Cycles 1 Status Bits These condition flags are modified only if the destinatio...

Page 528: ...UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Example 2 ANDN3 R1 AR5 IR0 R0 Before Instruction After Instruction R0 00 0000 0000 R0 00 0000 0F30 R1 00 0000 00CF R1 00 0000 00CF AR5 80 9825 AR5 80 982A IR0 5 IR0 5 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 809825h 0FFF 809825h 0FFF Note Cycle Count See Section 8 5 2 Data Loads and Stores on page 8 24 for the effects of opera...

Page 529: ...t operand is greater than 0 the dst operand is left shifted by the value of the count operand Low order bits that are shifted in are zero filled and high order bits are shifted out through the carry C bit Arithmetic left shift C dst 0 If the count operand is less than 0 the dst operand is right shifted by the abso lute value of the count operand The high order bits of the dst operand are sign exte...

Page 530: ...alue of the last bit shifted out 0 for a shift count of 0 OVM Operation is not affected by OVM bit value Example 1 ASH R1 R3 Before Instruction After Instruction R1 00 0000 0010 R1 00 0000 0010 R3 00 000A E000 R3 00 E000 0000 LUF 0 LUF 0 LV 0 LV 1 UF 0 UF 0 N 0 N 1 Z 0 Z 0 V 0 V 1 C 0 C 0 16 Example 2 ASH 98C3h R5 Before Instruction After Instruction R5 00 AEC0 0001 R5 00 FFFF FFAE DP 80 DP 80 LUF...

Page 531: ...perand are used to generate the 2s comple ment shift count of up to 32 bits If the count operand is greater than 0 the src operand is left shifted by the value of the count operand Low order bits that are shifted in are zero filled and high order bits are shifted out through the status register s C bit Arithmetic left shift C src 0 If the count operand is less than 0 the src operand is right shift...

Page 532: ...erated 0 otherwise V 1 if an integer overflow occurs 0 otherwise C Set to the value of the last bit shifted out 0 for a shift count of 0 OVM Operation is not affected by OVM bit value Example 1 ASH3 AR3 1 R5 R0 Before Instruction After Instruction R0 00 0000 0000 R0 00 02B0 0000 R5 00 0000 02B0 R5 00 0000 02B0 AR3 80 9921 AR3 80 9920 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 ...

Page 533: ...on After Instruction R1 00 FFFF FFF8 R1 00 FFFF FFF8 R3 00 FFFF CB00 R3 00 FFFF CB00 R5 00 0000 0000 R5 00 FFFF FFCB LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 1 Z 0 Z 0 V 0 V 0 C 0 C 0 8 8 Note Cycle Count See Section 8 5 2 Data Loads and Stores on page 8 5 2 for the effects of operand ordering on the cycle count ...

Page 534: ...register Rn2 0 n2 7 dst2 indirect disp 0 1 IR0 IR1 Opcode 31 24 23 16 8 7 0 15 1 1 0 1 0 0 1 dst1 count src3 dst2 src2 Description The seven LSBs of the count operand register are used to generate the 2s complement shift count of up to 32 bits If the count operand is greater than 0 the src2 operand is left shifted by the value of the count operand Low order bits shifted in are zero filled and high...

Page 535: ...d in parallel ASH3 writes to the same register STI ac cepts the contents of the register as input before it is modified by the ASH3 If src2 and dst2 point to the same location src2 is read before the write to dst2 Cycles 1 Status Bits These condition flags are modified only if the destination register is R7 R0 LUF Unaffected LV 1 if an integer overflow occurs unchanged otherwise UF 0 N MSB of the ...

Page 536: ... FFE8 R5 00 0000 0035 R5 00 0000 0035 AR2 80 98A2 AR2 80 98A2 AR6 80 9900 AR6 80 998C IR1 8C IR1 8C LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 809900h 0AE000000 809900h 0AE000000 8098A2h 0 8098A2h 35 24 24 53 53 53 Note Cycle Count See Section 8 5 2 Data Loads and Stores on page 8 24 for the effects of operand ordering on the cycle count ...

Page 537: ...ed register are loaded into the PC If the src operand is expressed in PC relative mode the assembler generates a displacement displacement label PC of branch instruction 1 This displacement is stored as a 16 bit signed integer in the 16 LSBs of the branch instruction word This displacement is added to the PC of the branch instruction plus 1 to generate the new PC The C3x provides 20 condition code...

Page 538: ...0 0003 FF00 PC 2B00 PC 3 FF00 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 1 Z 1 V 0 V 0 C 0 C 0 Note If a BZ instruction is executed immediately following a RND instruction with a 0 operand the branch is not performed because the 0 flag is not set To circumvent this problem execute a BZUF instead of a BZ instruction ...

Page 539: ...essing mode the contents of the specified register are loaded into the PC If the src operand is expressed in PC relative mode the assembler generates a displacement displacement label PC of branch instruction 3 This displacement is stored as a 16 bit signed integer in the 16 LSBs of the branch instruction This displacement is added to the PC of the branch in struction plus 3 to generate the new PC...

Page 540: ...C 0 C 0 Note Delayed branches disable interrupts until the completion of the three instruc tions that follow the delayed branch regardless if the branch is or is not per formed The following instructions cannot be used in the next three instruc tions following a delayed branch Bcond BcondD BR BRD CALL CALL cond DBcond DBcondD IDLE IDLE2 RETIcond RETScond RPTB RPTS TRAPcond ...

Page 541: ...ecution of the branch see Section 8 2 Pipeline Con flicts on page 8 4 An unconditional branch is performed The src operand is assumed to be a 24 bit unsigned integer Note that bit 24 0 for a standard branch Cycles 4 Status Bits LUF Unaffected LV Unaffected UF Unaffected N Unaffected Z Unaffected V Unaffected C Unaffected OVM Operation is not affected by OVM bit value Example BR 805Ch Before Instru...

Page 542: ...e PC is modified The effect is a single cycle branch An unconditional branch is performed The src operand is assumed to be a 24 bit unsigned integer Note that bit 24 1 for a delayed branch Cycles 1 Status Bits LUF Unaffected LV Unaffected UF Unaffected N Unaffected Z Unaffected V Unaffected C Unaffected OVM Operation is not affected by OVM bit value Example BRD 2Ch Before Instruction After Instruc...

Page 543: ... the PC The src operand is assumed to be a 24 bit unsigned immediate operand Since the CALL instruction takes 4 cycles to execute the pipeline is flushed Cycles 4 Status Bits LUF Unaffected LV Unaffected UF Unaffected N Unaffected Z Unaffected V Unaffected C Unaffected OVM Operation is not affected by OVM bit value Example CALL 123456h Before Instruction After Instruction PC 0005 PC 123456 SP 8098...

Page 544: ... assembler gener ates a displacement displacement label PC of call instruction 1 This displacement is stored as a 16 bit signed integer in the 16 LSBs of the call in struction word This displacement is added to the PC of the call instruction plus 1 to generate the new PC This instruction flushes the pipeline as shown in Example 8 13 on page 8 18 The C3x provides 20 condition codes that can be used...

Page 545: ...87 Assembly Language Instructions Example CALLNZ R5 Before Instruction After Instruction R5 00 0000 0789 R5 00 0000 0789 PC 0123 PC 0789 SP 809835 SP 809836 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 809836h 124 ...

Page 546: ... allows for nondestructive compares The dst and src operands are assumed to be floating point numbers Cycles 1 Status Bits These condition flags are modified for all destination registers R27 R0 LUF 1 if a floating point underflow occurs unchanged otherwise LV 1 if a floating point overflow occurs unchanged otherwise UF 1 if a floating point underflow occurs 0 otherwise N 1 if a negative result is...

Page 547: ...ns Example CMPF AR4 R6 Before Instruction After Instruction R6 07 0C80 0000 R6 07 0C80 0000 AR4 80 98F2 AR4 80 98F2 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 1 V 0 V 0 C 0 C 0 Data memory 8098F3h 070C8000 8098F3h 070C8000 1 4050e 02 1 4050e 02 1 4050e 02 1 4050e 02 ...

Page 548: ...ny register which allows for nondestructive compares The src1 and src2 operands are assumed to be floating point numbers Although this instruction has only two operands it is designated as a 3 operand instruction because op erands are specified in the 3 operand format Cycles 1 Status Bits These condition flags are modified for all destination registers R27 R0 LUF 1 if a floating point underflow oc...

Page 549: ...831 AR2 80 9831 AR3 80 9852 AR4 80 9851 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 1 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 809831h 77A7000 809831h 77A7000 809852h 57A2000 809852h 57A2000 2 5044e 02 2 5044e 02 6 253125e 01 6 253125e 01 Note Cycle Count See Section 8 5 2 Data Loads and Stores on page 8 24 for the effects of operand ordering on the cycle count ...

Page 550: ...s are assumed to be signed integers Cycles 1 Status Bits These condition flags are modified for all destination registers R27 R0 LUF Unaffected LV 1 if an integer overflow occurs unchanged otherwise UF 0 N 1 if a negative result is generated 0 otherwise Z 1 if a 0 result is generated 0 otherwise V 1 if an integer overflow occurs 0 otherwise C 1 if a borrow occurs 0 otherwise OVM Operation is not a...

Page 551: ...cted from the src1 operand The result is not loaded into any register which allows for nondestructive compares The src1 and src2 operands are assumed to be signed integers Although this instruction has only two operands it is designated as a 3 operand instruction because oper ands are specified in the 3 operand format Cycles 1 Status Bits These condition flags are modified for all destination regi...

Page 552: ...Instruction R4 00 0000 0898 R4 00 0000 0898 R7 00 0000 03E8 R7 00 0000 03E8 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 2200 1000 2200 1000 Note Cycle Count See Section 8 5 2 Data Loads and Stores on page 8 24 for the effects of operand ordering on the cycle count ...

Page 553: ...a 24 bit signed integer The 8 MSBs are un modified by the decrement operation The comparison of the auxiliary register uses only the 24 LSBs of the auxiliary register Note that the branch condition does not depend on the auxiliary register decrement If the src operand is expressed in register addressing mode the contents of the specified register are loaded into the PC If the src operand is expres...

Page 554: ...d Z Unaffected V Unaffected C Unaffected OVM Operation is not affected by OVM bit value Example CMPI 200 R3 DBLT AR3 R2 Before Instruction After Instruction R2 00 0000 009F R2 00 0000 009F R3 00 0000 0080 R3 00 0000 0080 AR3 00 0012 AR3 00 0011 PC 005F PC 009F LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 1 N 1 Z 0 Z 0 V 0 V 0 C 0 C 0 Mode Bit ...

Page 555: ...ree instructions following the DBcondD do not affect the condition The auxiliary register is treated as a 24 bit signed integer The 8 MSBs are un modified by the decrement operation The comparison of the auxiliary register uses only the 24 LSBs of the auxiliary register The branch condition does not depend on the auxiliary register decrement If the src operand is expressed in register addressing m...

Page 556: ...ted N Unaffected Z Unaffected V Unaffected C Unaffected OVM Operation is not affected by OVM bit value Example CMPI 26h R2 DBZD AR5 110h Before Instruction After Instruction R2 00 0000 0026 R2 00 0000 0026 AR5 00 0067 AR5 00 0066 PC 0100 PC 0210 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 1 V 0 V 0 C 0 C 0 Mode Bit ...

Page 557: ...d to be a floating point number and the dst operand a signed integer The exponent field of the dst register bits 39 32 is not modified Integer overflow occurs when the floating point number is too large to be repre sented as a 32 bit 2s complement integer In the case of integer overflow the result is saturated in the direction of overflow Cycles 1 Status Bits These condition flags are modified onl...

Page 558: ...ger Conversion 13 100 Example FIX R1 R2 Before Instruction After Instruction R1 0A 2820 0000 R1 0A 2820 0000 R2 00 0000 0000 R2 00 0000 0541 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 1 3454e 3 13454e 3 1345 ...

Page 559: ...de 31 24 23 16 8 7 0 15 1 1 0 1 0 1 dst1 src2 dst2 0 src3 0 0 0 Description A floating point to integer conversion is performed All registers are read at the beginning and loaded at the end of the execute cycle This means that if one of the parallel operations STI reads from a register and the operation being performed in parallel FIX writes to the same register STI accepts the contents of the reg...

Page 560: ...C Unaffected OVM Operation is not affected by OVM bit value Example FIX AR4 1 R1 STI R0 AR2 Before Instruction After Instruction R0 00 0000 00DC R0 00 0000 00DC R1 00 0000 0000 R1 00 0000 00B3 AR2 80 983C AR2 80 983C AR4 80 98A2 AR4 80 98A3 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 8098A3h 733C000 8098A3 733C000 80983Ch 0 80983C 0DC 220 1 7950e 02 220 179 1 79750e...

Page 561: ...iption The integer operand src is converted to the floating point value equal to it the result is loaded into the dst register The src operand is assumed to be a signed integer the dst operand is assumed to be a floating point number Cycles 1 Status Bits These condition flags are modified only if the destination register is R7 R0 LUF Unaffected LV Unaffected UF 0 N 1 if a negative result is genera...

Page 562: ...04 Example FLOAT AR2 2 R5 Before Instruction After Instruction R5 00 034C 2000 R5 00 72E0 0000 AR2 80 9800 AR2 80 9802 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 809802 0AE 809802 0AE 174 1 27578125e 01 1 74e 02 174 ...

Page 563: ... 1 dst1 src2 dst2 1 src3 0 0 0 Description An integer to floating point conversion is performed All registers are read at the beginning and loaded at the end of the execute cycle If one of the parallel operations STF reads from a register and the operation being performed in parallel FLOAT writes to the same register then STF accepts the contents of the register as input before it is modified by F...

Page 564: ...000 AR1 80 9933 AR1 80 9933 AR2 80 98C5 AR2 80 98C5 IR0 8 IR0 8 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 8098CD 0AE 8098CD 0AE 809933 0 809933 034C2000 174 1 27578125e 01 1 740e 02 174 1 27578125e 01 1 27578125e 01 Note Cycle Count See Section 8 5 2 Data Loads and Stores on page 8 24 for the effects of operand ordering on the cycle count ...

Page 565: ...f H1 cycle after the beginning of the decode phase of the IACK instruction At the first half of the H1 cycle of the completion of the dummy read IACK is set to 1 The IACK signal will not be extended due to multicycle reads with wait states This instruction can be used to generate an external interrupt acknowledge The IACK signal and the ad dress can be used to signal interrupt acknowledge to exter...

Page 566: ...IACK Interrupt Acknowledge 13 108 Example IACK AR5 Before Instruction After Instruction IACK 1 IACK 1 PC 300 PC 301 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 ...

Page 567: ...ed interrupt is received When the interrupt is received the contents of the PC are pushed onto the active system stack the interrupt vector is read and the interrupt service routine is executed Cycles 1 Status Bits LUF Unaffected LV Unaffected UF Unaffected N Unaffected Z Unaffected V Unaffected C Unaffected OVM Operation is not affected by OVM bit value Example IDLE The processor idles until a re...

Page 568: ...stop with H1 high and H3 low The device remains in IDLE2 until one of the four external interrupts INT3 INT0 is asserted for at least two H1 cycles When one of the four interrupts is asserted the clocks start after a delay of one H1 cycle The clocks can start up in the phase opposite that in which they were stopped that is H1 might start high when H3 was high before stopping and H3 might start hig...

Page 569: ...ions after a delayed branch should not be IDLE or IDLE2 instructions Cycles 1 Status Bits LUF Unaffected LV Unaffected UF Unaffected N Unaffected Z Unaffected V Unaffected C Unaffected OVM Operation is not affected by OVM bit value Example IDLE2 The processor idles until a reset or interrupt occurs Mode Bit ...

Page 570: ...the dst register No modification of the dst register mantissa field is made unless the value of the exponent loaded is the reserved value of the exponent for 0 as determined by the precision of the src operand Then the mantissa field of the dst register is set to 0 The src and dst operands are assumed to be float ing point numbers Immediate values are evaluated in the short floating point format C...

Page 571: ...e Instructions Example LDE R0 R5 Before Instruction After Instruction R0 02 0005 6F30 R0 02 0005 6F30 R5 0A 056F E332 R5 02 056F E332 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 4 00066337e 00 1 06749648e 03 4 00066337e 00 4 16990814e 00 ...

Page 572: ...loating point numbers Cycles 1 Status Bits These condition flags are modified only if the destination register is R7 R0 LUF Unaffected LV Unaffected UF 0 N 1 if a negative result is generated 0 otherwise Z 1 if a 0 result is generated 0 otherwise V 0 C Unaffected OVM Operation is not affected by OVM bit value Example LDF 9800h R2 Before Instruction After Instruction R2 00 0000 0000 R2 01 0C52 A000...

Page 573: ...to be floating point numbers The C3x provides 20 condition codes that can be used with this instruction see Table 13 12 on page 13 30 for a list of condition mnemonics condition codes and flags Note that an LDFU load floating point unconditionally in struction is useful for loading R7 R0 without affecting condition flags Condi tion flags are set on a previous instruction only when the destination ...

Page 574: ...13 116 Example LDFZ R3 R5 Before Instruction After Instruction R3 2C FF2C D500 R3 2C FF2C D500 R5 5F 0000 003E R5 2C FF2C D500 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 1 Z 1 V 0 V 0 C 0 C 0 1 77055560e 13 3 96140824e 28 1 77055560e 13 1 77055560e 13 ...

Page 575: ...nterlocked operation is sig naled over XF0 and XF1 The src and dst operands are assumed to be floating point numbers Only direct and indirect modes are allowed See Section 7 4 Interlocked Operations on page 7 13 for a detailed description Cycles 1 if XF1 0 see Section 7 4 on page 7 13 Status Bits These condition flags are modified only if the destination register is R7 R0 LUF Unaffected LV Unaffec...

Page 576: ...ample LDFI AR2 R7 Before Instruction After Instruction R7 00 0000 0000 R7 05 84C0 0000 AR2 80 98F1 AR2 80 98F1 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 8098F2h 584C000 8098F2h 584C000 6 28125e 01 6 28125e 01 6 28125e 01 ...

Page 577: ...silicon revision 2 0 or greater src1 indirect disp 0 1 IR0 IR1 dst1 register Rn1 0 n1 7 src2 indirect disp 0 1 IR0 IR1 or any CPU register dst2 register Rn2 0 n2 7 Opcode 31 2423 16 8 7 0 15 1 1 0 0 0 1 dst2 src2 src1 0 dst1 0 0 0 Description Two floating point loads are performed in parallel If the LDFs load the same register the assembler issues a warning The result is that of LDF src2 dst2 Cycl...

Page 578: ...7 0C80 0000 AR7 80 988A AR1 80 9857 IR0 8 AR7 80 988B LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 809857h 70C8000 809857h 70C8000 80988Ah 57B4000 80988Ah 57B4000 1 4050e 02 1 4050e 02 6 281250e 01 6 281250e 01 6 281250e 01 1 4050e 02 Note Cycle Count See Section 8 5 2 Data Loads and Stores on page 8 24 for the effects of operand ordering on the cycle count ...

Page 579: ...licon revision 2 0 or greater src2 indirect disp 0 1 IR0 IR1 or any CPU register dst1 register Rn1 0 n1 7 src3 register Rn2 0 n2 7 dst2 indirect disp 0 1 IR0 IR1 Opcode 31 2423 16 8 7 0 15 1 1 0 1 1 0 dst1 src2 dst2 0 0 0 0 src3 Description A floating point load and a floating point store are performed in parallel If src2 and dst2 point to the same location src2 is read before the write to dst2 Cy...

Page 580: ...98E7 AR2 80 98E6 AR4 80 9900 AR4 80 9910 IR1 10 IR1 10 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 8098E7h 70C8000 8098E7h 70C8000 809900h 0 809900h 57B4000 1 4050e 02 6 28125e 01 1 4050e 02 6 28125e 01 6 28125e 01 1 4050e 02 Note Cycle Count See Section 8 5 2 Data Loads and Stores on page 8 24 for the effects of operand ordering on the cycle count ...

Page 581: ... register The dst and src operands are assumed to be signed integers An alternate form of LDI LDP is used to load the data page pointer register DP See the LDP instruction in Section 13 6 2 Optional Assembler Syntax beginning on page 13 34 Cycles 1 Status Bits These condition flags are modified only if the destination register is R7 R0 LUF Unaffected LV Unaffected UF 0 N 1 if a negative result is ...

Page 582: ...24 Example LDI AR1 IR0 R5 Before Instruction After Instruction R5 00 0000 03C5 R5 00 0000 0026 AR1 2C AR1 2C IR0 5 IR0 5 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 27h 26 27h 26 965 38 38 38 ...

Page 583: ...and src operands are assumed to be signed integers The C3x provides 20 condition codes that can be used with this instruction see Table 13 12 on page 13 30 for a list of condition mnemonics condition codes and flags Note that an LDIU load integer unconditionally instruction is useful for loading R7 R0 without affecting the condition flags Condition flags are set on a previous instruction only when...

Page 584: ... 0000 0FE2 R6 00 0000 0FE2 AR0 80 98F0 AR0 80 98F1 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 8098F0h 027C 8098F0h 027C 4 066 4 066 636 636 Note Auxiliary Register Arithmetic The test condition does not affect the auxiliary register arithmetic AR modification always occurs ...

Page 585: ... operation is sig naled over XF0 and XF1 The src and dst operands are assumed to be signed integers Note that only the direct and indirect modes are allowed See Section 7 4 Interlocked Operations on page 7 13 for a detailed description Cycles 1 if XF 0 see Section 7 4 on page 7 13 Status Bits These condition flags are modified only if the destination register is R7 R0 LUF Unaffected LV Unaffected ...

Page 586: ...nterlocked 13 128 Example LDII 985Fh R3 Before Instruction After Instruction R3 00 0000 0000 R3 00 0000 00DC DP 80 DP 80 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 80985Fh 0DC 80985Fh 0DC ...

Page 587: ...C32 silicon revision 2 0 or greater src1 indirect disp 0 1 IR0 IR1 dst1 register Rn1 0 n1 7 src2 indirect disp 0 1 IR0 IR1 or any CPU register dst2 register Rn2 0 n2 7 Opcode 31 2423 16 8 7 0 15 1 1 0 0 0 1 dst2 src2 src1 1 dst1 0 0 0 Description Two integer loads are performed in parallel The assembler issues a warning if the LDIs load the same register The result is that of LDI src2 dst2 Cycles ...

Page 588: ...000 R7 00 0000 00FA AR1 80 9826 AR1 80 9826 AR7 80 98C8 AR7 80 98D8 IR0 10 IR0 10 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 809825h 0FA 809825h 0FA 8098C8h 2EE 8098C8h 2EE 250 750 250 750 750 250 Note Cycle Count See Section 8 5 2 Data Loads and Stores on page 8 24 for the effects of operand ordering on the cycle count ...

Page 589: ...32 silicon revision 2 0 or greater src2 indirect disp 0 1 IR0 IR1 or any CPU register dst1 register Rn1 0 n1 7 src3 register Rn2 0 n2 7 dst2 indirect disp 0 1 IR0 IR1 Opcode 31 2423 16 8 7 0 15 1 1 0 1 1 0 dst1 src2 dst2 1 0 0 0 src3 Description An integer load and an integer store are performed in parallel If src2 and dst2 point to the same location src2 is read before the dst2 is written Cycles ...

Page 590: ...00 0035 R7 00 0000 0035 AR1 80 98E7 AR1 80 98E7 AR5 80 982C AR5 80 9834 IR0 8 IR0 8 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 8098E6h 0DC 8098E6h 0DC 80982Ch 0 80982Ch 35 220 53 220 53 220 53 Note Cycle Count See Section 8 5 2 Data Loads and Stores on page 8 24 for the effects of operand ordering on the cycle count ...

Page 591: ...d is not modified The src and dst operands are assumed to be floating point numbers If the src operand is from memory the entire memory contents are loaded as the mantissa If immediate address ing mode is used bits 15 12 of the instruction word are forced to 0 by the as sembler Cycles 1 Status Bits LUF Unaffected LV Unaffected UF Unaffected N Unaffected Z Unaffected V Unaffected C Unaffected OVM O...

Page 592: ...ess essentially only bits 23 16 of src are used These eight bits are loaded into the eight LSBs of the data page pointer The eight LSBs of the pointer are used in direct addressing as a pointer to the page of data being addressed There is a total of 256 pages each page 64K words long Bits 31 8 of the pointer are reserved and should be kept set to 0 Cycles 1 Status Bits LUF Unaffected LV Unaffected...

Page 593: ...y of 32 MHz performs in the same way as a 2 MHz C3x device which has an instruction cycle time of 1000 ns This allows for low power operation The C3x CPUs slow down during the read phase of the LOPOWER instruc tion To exit the LOPOWER power down mode invoke the MAXSPEED instruction opcode 1080 0000 h The C3x resumes full speed operation during the read phase of the MAXSPEED instruction Do not run ...

Page 594: ...dst operand is left shifted by the value of the count operand Low order bits shifted in are zero filled and high order bits are shifted out through the carry C bit Logical left shift C dst 0 If the count operand is less than 0 the dst is right shifted by the absolute value of the count operand The high order bits of the dst operand are zero filled as they are shifted to the right Low order bits ar...

Page 595: ...shift count of 0 OVM Operation is not affected by OVM bit value Example 1 LSH R4 R7 Before Instruction After Instruction R4 00 0000 0018 R4 00 0000 0018 R7 00 0000 02AC R7 00 AC00 0000 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 1 Z 0 Z 0 V 0 V 1 C 0 C 0 24 24 Example 2 LSH AR5 IR1 R5 Before Instruction After Instruction R5 00 12C0 0000 R5 00 0001 2C00 AR5 80 9908 AR5 80 9908 IR0 4 IR0 4 LUF 0 LUF 0 LV ...

Page 596: ...ft count If the count operand is greater than 0 a copy of the src operand is left shifted by the value of the count operand and the result is written to the dst The src is not changed Low order bits shifted in are zero filled and high order bits are shifted out through the carry C bit Logical left shift C src 0 If the count operand is less than 0 the src operand is right shifted by the abso lute v...

Page 597: ... a 0 output is generated 0 otherwise V 0 C Set to the value of the last bit shifted out 0 for a shift count of 0 unaffected if dst is not R7 R0 OVM Operation is not affected by OVM bit value Example 1 LSH3 R4 R7 R2 Before Instruction After Instruction R2 00 0000 0000 R2 00 AC00 0000 R4 00 0000 0018 R4 00 0000 0018 R7 00 0000 02AC R7 00 0000 02AC LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 1 Z 0 Z 0 V 0 ...

Page 598: ...00 0001 2C00 R5 00 12C0 0000 R5 00 12C0 0000 AR4 80 9908 AR4 80 9908 IR1 4 IR1 4 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 809904h 0FFFFFFF4 809904h 0FFFFFFF4 12 12 Note Cycle Count See Section 8 5 2 Data Loads and Stores on page 8 24 for the effects of operand ordering on the cycle count ...

Page 599: ...n2 0 n2 7 dst2 indirect disp 0 1 IR0 IR1 Opcode 31 2423 16 8 7 0 15 1 1 0 1 1 1 dst1 src2 dst2 0 count src3 Description The seven LSBs of the count operand are used to generate the 2s comple ment shift count If the count operand is greater than 0 a copy of the src2 operand is left shifted by the value of the count operand and the result is written to the dst1 The src2 is not changed Low order bits...

Page 600: ...ations STI reads from a register and the operation being performed in parallel LSH3 writes to the same register STI accepts as input the contents of the register before it is modified by the LSH3 If src2 and dst2 point to the same location src2 is read before dst2 is written Cycles 1 Status Bits These condition flags are modified only if the destination register is R7 R0 LUF Unaffected LV Unaffect...

Page 601: ... Instruction After Instruction R0 00 0000 0000 R0 00 AC00 0000 R2 00 0000 0018 R2 00 0000 0018 R4 00 0000 00DC R4 00 0000 00DC AR3 80 98C2 AR3 80 98C3 AR5 80 98A3 AR5 80 98A3 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 8098C3h 0AC 8098C3h 0AC 8098A2h 0 8098A2h 0DC 24 24 220 220 220 ...

Page 602: ...00 0002 C000 R7 00 FFFF FFF4 R7 00 FFFF FFF4 AR0 80 98B7 AR0 80 98B7 AR2 80 9863 AR2 80 9862 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 809863h 2C000000 809863h 2C000000 8098B8h 0 8098B8h 12C 300 300 12 12 300 Note Cycle Count See Section 8 5 2 Data Loads and Stores on page 8 24 for the effects of operand ordering on the cycle count ...

Page 603: ... 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description Exits LOPOWER power down mode invoked by LOPOWER instruction with opcode 10800001h The LC31 or C32 resumes full speed operation during the read phase of the MAXSPEED instruction Cycles 1 Status Bits LUF Unaffected LV Unaffected UF Unaffected N Unaffected Z Unaffected V Unaffected C Unaffected OVM Operation is not affected by OVM bit value Ex...

Page 604: ...Status Bits These condition flags are modified only if the destination register is R7 R0 LUF 1 if a floating point underflow occurs unchanged otherwise LV 1 if a floating point overflow occurs unchanged otherwise UF 1 if a floating point underflow occurs 0 otherwise N 1 if a negative result is generated 0 otherwise Z 1 if a 0 result is generated 0 otherwise V 1 if a floating point overflow occurs ...

Page 605: ...tion The product of the src1 and src2 operands is loaded into the dst register The src1 and src2 operands are assumed to be single precision floating point numbers and the dst operand is an extended precision floating point number Cycles 1 Status Bits These condition flags are modified only if the destination register is R7 R0 LUF 1 if a floating point underflow occurs unchanged otherwise LV 1 if ...

Page 606: ... 6 281250e 01 1 79750e 02 Example 2 MPYF3 AR2 IR0 R7 R2 or MPYF3 R7 AR2 IR0 R2 Before Instruction After Instruction R2 00 0000 0000 R2 0D 09E4 A000 R7 05 7B40 0000 R7 05 7B40 0000 AR2 80 9800 AR2 80 9800 IR0 12A IR0 12A LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 80992Ah 70C8000 80992Ah 70C8000 8 82515625e 03 6 281250e 01 1 4050e 02 6 281250e 01 1 4050e 02 Note Cycl...

Page 607: ...Operation srcA srcB dst1 srcC srcD dst2 Operands srcA srcB srcC srcD Any two indirect disp 0 1 IR0 IR1 Any two register 0 vRn v7 dst1 register d1 0 R0 1 R1 dst2 register d2 0 R2 1 R3 src1 register Rn 0 n 7 src2 register Rn 0 n 7 src3 indirect disp 0 1 IR0 IR1 src4 indirect disp 0 255 IR0 IR1 P parallel addressing modes 0 P 3 ...

Page 608: ... 1 1 2 2 dst1 register d1 0 R0 1 R1 dst2 register d2 0 R2 1 R3 src1 register Rn 0 n 7 src2 register Rn 0 n 7 src3 indirect disp 0 1 IR0 IR1 or any CPU register src4 indirect disp 0 1 IR0 IR1 or any CPU register P parallel addressing modes 0 P 3 Version 4 7 or earlier of TMS320 floating point code generation tools P srcA srcB srcD srcC 00 src4 src3 src1 src2 01 src3 src1 src4 src2 10 src1 src2 src3...

Page 609: ...ion of addressing modes can be coded for the four possible source operands as long as two are coded as indirect and two are coded as register The assignment of the source operands srcA srcD to the src1 src4 fields varies depending on the combination of addressing modes used and the P field is encoded accordingly If src2 and dst2 point to the same location src2 is read before the write to dst2 Cycl...

Page 610: ... Section 8 5 Clocking Memory Accesses on page 8 24 Before Instruction After Instruction R0 00 0000 0000 R0 04 6718 0000 R3 00 0000 0000 R3 08 2020 0000 R5 07 33C0 0000 R5 07 33C0 0000 R7 07 0C80 0000 R7 07 0C80 0000 AR1 80 98A8 AR1 80 98A4 AR5 80 98C5 AR5 80 98C6 IR0 4 IR0 4 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 8098C5h 34C0000 8098C5h 34C0000 8098A4h 1110000 ...

Page 611: ... 0 1 IR0 IR1 or any CPU register dst1 register Rn2 0 n2 7 src3 register Rn3 0 n3 7 dst2 indirect disp 0 1 IR0 IR1 Opcode 31 24 23 16 8 7 0 15 1 1 0 1 1 1 dst1 src2 dst2 1 src1 src3 Description A floating point multiplication and a floating point store are performed in paral lel All registers are read at the beginning and loaded at the end of the execute cycle If one of the parallel operations MPYF...

Page 612: ...fected OVM Operation is not affected by OVM bit value Example MPYF3 AR2 1 R7 R0 STF R3 AR0 IR0 Before Instruction After Instruction R0 00 0000 0000 R0 0D 09E4 A000 R3 08 6B28 0000 R3 08 6B28 0000 R7 05 7B40 0000 R7 05 7B40 0000 AR0 80 9860 AR0 80 9858 AR2 80 982B AR2 80 982B IR0 8 IR0 8 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 80982Ah 70C8000 80982Ah 70C8000 8098...

Page 613: ...2 Operation srcA srcB dst1 srcD srcC dst2 Operands srcA srcB srcC srcD Any two register 0 Rn 7 Any two indirect disp 0 1 IR0 IR1 dst1 register d1 0 R0 1 R1 dst2 register d2 0 R2 1 R3 src1 register Rn 0 n 7 src2 register Rn 0 n 7 src3 indirect disp 0 1 IR0 IR1 src4 indirect disp 0 1 IR0 IR1 P parallel addressing modes 0 P 3 ...

Page 614: ...d1 0 R0 1 R1 dst2 register d2 0 R2 1 R3 src1 register Rn 0 n 7 src2 register Rn 0 n 7 src3 indirect disp 0 1 IR0 IR1 or any CPU register src4 indirect disp 0 1 IR0 IR1 or any CPU register P parallel addressing modes 0 P 3 Version 4 7 or earlier of TMS320 floating point code generation tools P srcA srcB srcD srcC 00 src4 src3 src1 src2 01 src3 src1 src4 src2 10 src1 src2 src3 src4 11 src3 src1 src2...

Page 615: ...contents of the register before it is modified by the SUBF3 Any combination of addressing modes can be coded for the four possible source operands as long as two are coded as indirect and two are coded regis ter The assignment of the source operands srcA srcD to the src1 src4 fields varies depending on the combination of addressing modes used and the P field is encoded accordingly Cycles 1 Note Cy...

Page 616: ...ot affected by OVM bit value Example MPYF3 R5 AR7 IR1 R0 SUBF3 R7 AR3 1 R2 or MPYF3 AR7 IR1 R5 R0 SUBF3 R7 AR3 1 R2 Before Instruction After Instruction R0 00 0000 0000 R0 04 6718 0000 R2 00 0000 0000 R2 05 E300 0000 R5 03 4C00 0000 R5 03 4C00 0000 R7 07 33C0 0000 R7 07 33C0 0000 AR3 80 98B2 AR3 80 98B1 AR7 80 9904 AR7 80 990C IR1 8 IR1 8 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0...

Page 617: ...be 24 bit signed integers The result is assumed to be a 48 bit signed integer The output to the dst register is the 32 LSBs of the result Integer overflow occurs when any of the 16 MSBs of the 48 bit result differs from the MSB of the 32 bit output value Cycles 1 Status Bits These condition flags are modified only if the destination register is R7 R0 LUF Unaffected LV 1 if an integer overflow occu...

Page 618: ...60 Example MPYI R1 R5 Before Instruction After Instruction R1 00 0033 C251 R1 00 0033 C251 R5 00 0078 B600 R5 00 E21D 9600 LUF 0 LUF 0 LV 0 LV 1 UF 0 UF 0 N 0 N 1 Z 0 Z 0 V 0 V 1 C 0 C 0 3 392 081 7 910 912 501 377 536 3 392 081 ...

Page 619: ... and src2 operands is loaded into the dst register The src1 and src2 operands are assumed to be 24 bit signed integers The result is assumed to be a signed 48 bit integer The output to the dst register is the 32 LSBs of the result Integer overflow occurs when any of the 16 MSBs of the 48 bit result differs from the MSB of the 32 bit output value Cycles 1 Status Bits These condition flags are modif...

Page 620: ...AD 809850h 0AD 8098F2h 0DC 8098F2h 0DC 173 38 060 220 173 220 Example 2 MPYI3 AR4 IR0 R2 R7 Before Instruction After Instruction R2 00 0000 00C8 R2 00 0000 00C8 R7 00 0000 0000 R7 00 0000 2710 AR4 80 99F8 AR4 80 99F0 IR0 8 IR0 8 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 8099F0h 32 8099F0h 32 200 200 50 50 10 000 Note Cycle Count See Section 8 5 2 Data Loads and St...

Page 621: ...srcC dst2 Operands srcA srcB srcC srcD Any two indirect disp 0 1 IR0 IR1 Any two register 0 vRn v7 srcA srcB srcC srcD can be one of the following combinations dst1 register d1 0 R0 1 R1 dst2 register d2 0 R2 1 R3 src1 register Rn 0 n 7 src2 register Rn 0 n 7 src3 indirect disp 0 1 IR0 IR1 src4 indirect disp 0 1 IR0 IR1 P parallel addressing modes 0 P 3 ...

Page 622: ...d1 0 R0 1 R1 dst2 register d2 0 R2 1 R3 src1 register Rn 0 n 7 src2 register Rn 0 n 7 src3 indirect disp 0 1 IR0 IR1 or any CPU register src4 indirect disp 0 1 IR0 IR1 or any CPU register P parallel addressing modes 0 P 3 Version 4 7 or earlier of TMS320 floating point code generation tools P srcA srcB srcD srcC 00 src4 src3 src1 src2 01 src3 src1 src4 src2 10 src1 src2 src4 src4 11 src3 src1 src2...

Page 623: ...des can be coded for the four possible source operands as long as two are coded as indirect and two are coded as register The assignment of the source operands srcA srcD to the src1 src4 fields varies depending on the combination of addressing modes used and the P field is encoded accordingly To simplify processing when the order is not significant the assembler may change the order of operands in...

Page 624: ...UF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 80981Eh 0FFFFFFCB 80981Eh 0FFFFFFCB 80996Eh 35 80996Eh 35 100 2000 53 53 100 53 20 20 53 Note Cycle Count One cycle if src3 and src4 are in internal memory src3 is in internal memory and src4 is in external memory Two cycles if src3 is in external memory and src4 is in internal memory src3 and src4 are in external memory For more...

Page 625: ...2 0 n2 7 src3 register Rn3 0 n3 7 dst2 indirect disp 0 1 IR0 IR1 Opcode 31 2423 16 8 7 0 15 1 1 1 0 0 0 dst1 src2 dst2 0 src1 src3 Description An integer multiplication and an integer store are performed in parallel All reg isters are read at the beginning and loaded at the end of the execute cycle If one of the parallel operations STI reads from a register and the operation be ing performed in pa...

Page 626: ...ted OVM Operation is affected by OVM bit value Example MPYI3 AR0 1 R5 R7 STI R2 AR3 1 Before Instruction After Instruction R2 00 0000 00DC R2 00 0000 00DC R5 00 0000 0032 R5 00 0000 0032 R7 00 0000 0000 R7 00 0000 2710 AR0 80 995A AR0 80 995B AR3 80 982F AR3 80 982F LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 80995Bh 0C8 80995Bh 0C8 80982Eh 0 80982Eh ODC 220 220 200...

Page 627: ...srcC dst2 Operands srcA srcB srcC srcD Any two indirect disp 0 1 IR0 IR1 Any two register 0 vRn v7 srcA srcB srcC srcD can be one of the following combinations dst1 register d1 0 R0 1 R1 dst2 register d2 0 R2 1 R3 src1 register Rn 0 n 7 src2 register Rn 0 n 7 src3 indirect disp 0 1 IR0 IR1 src4 indirect disp 0 1 IR0 IR1 P parallel addressing modes 0 P 3 ...

Page 628: ...rect disp 0 1 IR0 IR1 Any CPU Register 2 2 2 1 1 2 2 dst1 register d1 0 R0 1 R1 dst2 register d2 0 R2 1 R3 src1 register Rn 0 n 7 src2 register Rn 0 n 7 src3 indirect disp 0 1 IR0 IR1 or any CPU register src4 indirect disp 0 1 IR0 IR1 or any CPU register P parallel addressing modes 0 P 3 Version 4 7 or earlier of TMS320 floating point code generation tools P srcA srcB srcD srcC 00 src4 src3 src1 s...

Page 629: ...e four possible source operands as long as two are coded as indirect and two are coded as reg ister The assignment of the source operands srcA srcD to the src1 src4 fields varies depending on the combination of addressing modes used and the P field is encoded accordingly To simplify processing when the order is not sig nificant the assembler may change the order of operands in commutative op erati...

Page 630: ...IR1 0C LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 8098E4h 62 8098E4h 62 8099FCh 4B0 8099FCh 4B0 2000 4900 98 2000 50 800 1200 98 1200 Note Cycle Count One cycle if src3 and src4 are in internal memory src3 is in internal memory and src4 is in external memory Two cycles if src3 is in external memory and src4 is in internal memory src3 and src4 are in external memory...

Page 631: ...sumed to be signed integers Cycles 1 Status Bits These condition flags are modified only if the destination register is R7 R0 LUF Unaffected LV 1 if an integer overflow occurs unchanged otherwise UF 0 N 1 if a negative result is generated 0 otherwise Z 1 if a 0 result is generated 0 otherwise V 1 if an integer overflow occurs 0 otherwise C 1 if a borrow occurs 0 otherwise OVM Operation is affected...

Page 632: ...ister The dst and src operands are assumed to be floating point numbers Cycles 1 Status Bits These condition flags are modified only if the destination register is R7 R0 LUF 1 if a floating point underflow occurs unchanged otherwise LV 1 if a floating point overflow occurs unchanged otherwise UF 1 if a floating point underflow occurs 0 otherwise N 1 if a negative result is generated 0 otherwise Z ...

Page 633: ... Example NEGF AR3 2 R1 Before Instruction After Instruction R1 05 7B40 0025 R1 07 F380 0000 AR3 80 9800 AR3 80 9802 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 809802h 70C8000 809802h 70C8000 6 28125006e 01 1 4050e 02 1 4050e 02 1 4050e 02 ...

Page 634: ...re read at the beginning and loaded at the end of the execute cycle This means that if one of the parallel operations STF reads from a reg ister and the operation being performed in parallel NEGF writes to the same register STF accepts the contents of the register as input before it is modified by the NEGF If src2 and dst2 point to the same location src2 is read before the write to dst2 Cycles 1 S...

Page 635: ...84C0 0000 AR4 80 98E1 AR4 80 98E0 AR5 80 9803 AR5 80 9804 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 8098E1h 57B400000 8098E1h 57B4000 809804h 0 809804h 733C000 6 281250e 01 1 79750e 02 6 281250e 01 1 79750e 02 1 79750e 02 6 281250e 01 Note Cycle Count See subsection 8 5 2 Data Loads and Stores on page 8 24 for the effects of operand ordering on the cycle count ...

Page 636: ... be signed integers Cycles 1 Status Bits These condition flags are modified only if the destination register is R7 R0 LUF Unaffected LV 1 if an integer overflow occurs unchanged otherwise UF 0 N 1 if a negative result is generated 0 otherwise Z 1 if a 0 result is generated 0 otherwise V 1 if an integer overflow occurs 0 otherwise C 1 if a borrow occurs 0 otherwise OVM Operation is affected by OVM ...

Page 637: ... and an integer store are performed in parallel All registers are read at the beginning and loaded at the end of the execute cycle If one of the parallel operations STI reads from a register and the operation being performed in parallel NEGI writes to the same register STI accepts the con tents of the register as input before it is modified by the NEGI If src2 and dst2 point to the same location s...

Page 638: ...00 FFFF FF24 AR1 80 98A5 AR1 80 98A6 AR3 80 982F AR3 80 982F LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 1 Z 0 Z 0 V 0 V 0 C 0 C 1 Data memory 80982Eh 0DC 80982Eh 0DC 8098A5h 0 8098A5h 19 25 220 220 220 25 Note Cycle Count See subsection 8 5 2 Data Loads and Stores on page 8 24 for the effects of operand ordering on the cycle count ...

Page 639: ... 0 0 0 0 Description If the src operand is specified in the indirect mode the specified addressing operation is performed and a dummy memory read occurs If the src operand is omitted no operation is performed Cycles 1 Status Bits LUF Unaffected LV Unaffected UF Unaffected N Unaffected Z Unaffected V Unaffected C Unaffected OVM Operation is not affected by OVM bit value Example 1 NOP Before Instruc...

Page 640: ...assumed to be a normalized floating point number If src exp 128 and src man 0 then dst 0 Z 1 and UF 0 If src exp 128 and src man 0 then dst 0 Z 0 and UF 1 For all other cases of the src if a floating point underflow occurs then dst man is forced to 0 and dst exp 128 If src man 0 then dst man 0 and dst exp 128 Refer to Section 5 7 Normalization Using the NORM Instruction on page 5 37 for more infor...

Page 641: ...embly Language Instructions Example NORM R1 R2 Before Instruction After Instruction R1 04 0000 3AF5 R1 04 0000 3AF5 R2 07 0C80 0000 R2 F2 6BD4 0000 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 1 12451613e 04 ...

Page 642: ... The bitwise logical complement of the src operand is loaded into the dst regis ter The complement is formed by a logical NOT of each bit of the src operand The dst and src operands are assumed to be unsigned integers Cycles 1 Status Bits These condition flags are modified only if the destination register is R7 R0 LUF Unaffected LV Unaffected UF 0 N MSB of the output Z 1 if a 0 result is generated...

Page 643: ...5 Assembly Language Instructions Example NOT 982Ch R4 Before Instruction After Instruction R4 00 0000 0000 R4 00 FFFF A1D0 DP 080 DP 080 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 1 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 80982Ch 5E2F 80982Ch 5E2F ...

Page 644: ...c3 0 0 0 Description A bitwise logical NOT and an integer store are performed in parallel All regis ters are read at the beginning and loaded at the end of the execute cycle This means that if one of the parallel operations STI reads from a register and the operation being performed in parallel NOT writes to the same register STI accepts the contents of the register as input before it is modified ...

Page 645: ...F F3D0 R7 00 0000 00DC R7 00 0000 00DC AR2 80 99CB AR2 80 99CB AR4 80 9850 AR4 80 9840 IR1 10 IR1 10 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 1 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 8099CCh 0C2F 8099CCh 0C2F 809840h 0 809840h 0DC 220 220 220 Note Cycle Count See subsection 8 5 2 Data Loads and Stores on page 8 24 for the effects of operand ordering on the cycle count ...

Page 646: ... 0 0 0 1 0 0 0 0 0 dst src G Description The bitwise logical OR between the src and dst operands is loaded into the dst register The dst and src operands are assumed to be unsigned integers Cycles 1 Status Bits These condition flags are modified only if the destination register is R7 R0 LUF Unaffected LV Unaffected UF 0 N MSB of the output Z 1 if a 0 result is generated 0 otherwise V 0 C Unaffecte...

Page 647: ...age Instructions Example OR AR1 IR1 R2 Before Instruction After Instruction R2 00 1256 0000 R2 00 1256 2BCD AR1 80 9800 AR1 80 9804 IR1 4 IR1 4 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 809804h 2BCD 809804h 2BCD ...

Page 648: ...IR1 1 1 indirect disp 0 1 IR0 IR1 dst register Rn 0 n 27 Opcode 31 24 23 16 8 7 0 15 0 0 1 0 0 1 0 1 1 dst src2 T src1 Description The bitwise logical OR between the src1 and src2 operands is loaded into the dst register The src1 src2 and dst operands are assumed to be unsigned in tegers Cycles 1 Status Bits These condition flags are modified only if the destination register is R7 R0 LUF Unaffecte...

Page 649: ...ion R2 00 1256 0000 R2 00 1256 0000 R7 00 0000 0000 R7 0 1256 2BCD AR1 80 9800 AR1 80 9804 IR1 4 IR1 4 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 809804h 2BCD 809804h 2BCD Note Cycle Count See subsection 8 5 2 Data Loads and Stores on page 8 24 for the effects of operand ordering on the cycle count ...

Page 650: ...0 IR1 or any CPU register dst1 register Rn2 0 n2 7 src3 register Rn3 0 n3 7 dst2 indirect disp 0 1 IR0 IR1 Opcode 31 24 23 16 8 7 0 15 1 1 0 1 0 0 src1 src2 dst2 1 dst1 src3 A bitwise logical OR and an integer store are performed in parallel All registers are read at the beginning and loaded at the end of the execute cycle This means that if one of the parallel operations STI reads from a register...

Page 651: ...y OVM bit value Example OR3 AR2 R5 R2 STI R6 AR1 Before Instruction After Instruction R2 00 0000 0000 R2 00 0080 9800 R5 00 0080 0000 R5 00 0080 0000 R6 00 0000 00DC R6 00 0000 00DC AR1 80 9883 AR1 80 9882 AR2 80 9830 AR2 80 9831 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 809831h 9800 809831h 9800 809883h 0 809883h 0DC 220 220 220 Note Cycle Count See subsection 8 ...

Page 652: ... bits of an extended precision register R7 R0 are left unmodified Cycles 1 Status Bits These condition flags are modified only if the destination register is R7 R0 LUF Unaffected LV Unaffected UF 0 N 1 if a negative result is generated 0 otherwise Z 1 if a 0 result is generated 0 otherwise V 0 C Unaffected OVM Operation is not affected by OVM bit value Example POP R3 Before Instruction After Instr...

Page 653: ...r The eight LSBs of an extended precision register R7 R0 are zero filled Cycles 1 Status Bits These condition flags are modified only if the destination register is R7 R0 LUF Unaffected UF 0 LV Unaffected N 1 if a negative result is generated 0 otherwise Z 1 if a 0 result is generated 0 otherwise V 0 C Unaffected OVM Operation is not affected by OVM bit value Example POPF R4 Before Instruction Aft...

Page 654: ...nt of the stack pointer The integer or mantissa portion of an ex tended precision register R7 R0 is saved with this instruction Cycles 1 Status Bits LUF Unaffected LV Unaffected UF Unaffected N Unaffected Z Unaffected V Unaffected C Unaffected OVM Operation is not affected by OVM bit value Example PUSH R6 Before Instruction After Instruction R6 02 5C12 8081 R6 02 5C12 8081 SP 8098AE SP 8098AF LUF ...

Page 655: ... with a preincrement of the stack pointer The eight LSBs of the mantis sa are not saved Note the difference in R2 and the value on the stack in the example below Cycles 1 Status Bits LUF Unaffected LV Unaffected UF Unaffected N Unaffected Z Unaffected V Unaffected C Unaffected OVM Operation is not affected by OVM bit value Example PUSHF R2 Before Instruction After Instruction R2 02 5C12 8081 R2 02...

Page 656: ...of enabling all interrupts for which the corresponding interrupt enable bit is a 1 The C3x provides 20 condition codes that can be used with this instruction see Table 13 12 on page 13 30 for a list of condition mnemonics condition codes and flags Condition flags are set on a previous instruction only when the destination register is one of the extended precision registers R7 R0 or when one of the...

Page 657: ...ond 13 199 Assembly Language Instructions Example RETINZ Before Instruction After Instruction PC 0456 PC 0123 SP 809830 SP 80982F ST 0 ST 2000 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 809830h 123 809830h 123 ...

Page 658: ...es 20 condition codes that you can use with this instruction see Table 13 12 on page 13 30 for a list of condition mnemonics condition codes and flags Condition flags are set on a previous instruction only when the destination register is one of the extended precision registers R7 R0 or when one of the compare instructions CMPF CMPF3 CMPI CMPI3 TSTB or TSTB3 is executed Cycles 4 Status Bits LUF Un...

Page 659: ...y RETScond 13 201 Assembly Language Instructions Example RETSGE Before Instruction After Instruction PC 0123 PC 0456 SP 80983C SP 80983B LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 80983Ch 456 80983Ch 456 ...

Page 660: ...n floating point value If the src operand is exactly halfway between two single precision values it is rounded to the most positive value Cycles 1 Status Bits These condition flags are modified only if the destination register is R7 R0 LUF 1 if a floating point underflow occurs unchanged otherwise LV 1 if a floating point overflow occurs unchanged otherwise UF 1 if a floating point underflow occur...

Page 661: ...07 33C1 6EEF LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 1 79755599e 02 1 79755599e 02 1 79755600e 02 Note BZUF Instruction If a BZ instruction is executed immediately following an RND instruction with a 0 operand the branch is not performed because the zero flag is not set To circumvent this problem execute a BZUF instruction instead of a BZ instruction ...

Page 662: ...sferred into the carry C bit and the LSB Rotate left C dst Cycles 1 Status Bits These condition flags are modified only if the destination register is R7 R0 LUF Unaffected LV Unaffected UF 0 N MSB of the output Z 1 if a 0 output is generated 0 otherwise V 0 C Set to the value of the bit rotated out of the high order bit unaffected if dst is not R7 R0 OVM Operation is not affected by OVM bit value ...

Page 663: ...the same time the carry bit is transferred to the LSB Rotate left through carry bit C dst Cycles 1 Status Bits These condition flags are modified only if the destination register is R7 R0 LUF Unaffected LV Unaffected UF 0 N MSB of the output Z 1 if a 0 output is generated 0 otherwise V 0 C Set to the value of the bit rotated out of the high order bit if dst is not R7 R0 then C is shifted into the ...

Page 664: ...ROLC Rotate Left Through Carry 13 206 Example 2 ROLC R3 Before Instruction After Instruction R3 00 8000 4281 R3 00 0000 8502 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 1 ...

Page 665: ...nto the carry C bit and also transferred into the MSB Rotate right C dst Cycles 1 Status Bits These condition flags are modified only if the destination register is R7 R0 LUF Unaffected LV Unaffected UF 0 N MSB of the output Z 1 if a 0 output is generated 0 otherwise V 0 C Set to the value of the bit rotated out of the high order bit unaffected if dst is not R7 R0 OVM Operation is not affected by ...

Page 666: ...he dst while at the same time the dst LSB is rotated into the carry bit Rotate right through carry bit dst C Cycles 1 Status Bits These condition flags are modified only if the destination register is R7 R0 LUF Unaffected LV Unaffected UF 0 N MSB of the output Z 1 if a 0 output is generated 0 otherwise V 0 C Set to the value of the bit rotated out of the high order bit if dst is not R7 R0 then C i...

Page 667: ...is a 24 bit unsigned immediate value that is loaded into the repeat end address RE register A 1 is written into the re peat mode bit of status register ST RM to indicate that the PC is being up dated in the repeat mode The address of the next instruction is loaded into the repeat start address RS register RE should be greater than or equal to RS RE w RS Otherwise the code does not repeat even thou...

Page 668: ...owing two rules apply Rule 1 The last instruction in the block or the only instruction in a block of size 1 cannot be a Bcond BR DBcond CALL CALLcond TRAPcond RETIcond RETScond IDLE IDLE2 RPTB or RPTS Example 7 3 on page 7 6 shows an incorrectly placed standard branch Rule 2 None of the last four instructions at the bottom of the block or the only instruction in a block of size 1 can be a BcondD B...

Page 669: ...IR thus avoiding repeated memory access The src operand is loaded into the repeat counter RC A 1 is written into the repeat mode bit of the status register ST RM A 1 is also written into the re peat single bit S This indicates that the program fetches are to be performed only from the instruction register The next PC is loaded into the repeat end ad dress RE register and the repeat start address R...

Page 670: ... 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Because the block repeat modes modify the program counter no other instruction can modify the program counter at the same time Therefore the repeated instruction cannot be a Bcond BR DBcond CALL CALLcond TRAPcond RETIcond RETScond IDLE IDLE2 RPTB or RPTS If this rule is violated the PC will be undefined Note The RPTS instruction cannot be interrupted because instruction ...

Page 671: ...ation is signaled over XF0 and XF1 After the interlocked operation is acknowledged the interlocked operation ends SIGI ignores the external ready signals Refer to Section 7 4 Interlocked Operations on page 7 13 for detailed information Cycles 1 Status Bits LUF Unaffected LV Unaffected UF Unaffected N Unaffected Z Unaffected V Unaffected C Unaffected OVM Operation is not affected by OVM bit value E...

Page 672: ...ocation The src and dst oper ands are assumed to be floating point numbers Cycles 1 Status Bits LUF Unaffected LV Unaffected UF Unaffected N Unaffected Z Unaffected V Unaffected C Unaffected OVM Operation is not affected by OVM bit value Example STF R2 98A1h Before Instruction After Instruction R2 05 2C50 1900 R2 05 2C50 1900 DP 080 DP 080 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C ...

Page 673: ...ion is signaled over pins XF0 and XF1 The src and dst operands are assumed to be floating point numbers Refer to Section 7 4 Interlocked Operations on page 7 13 for detailed information Cycles 1 Status Bits LUF Unaffected LV Unaffected UF Unaffected N Unaffected Z Unaffected V Unaffected C Unaffected OVM Operation is not affected by OVM bit value Example STFI R3 AR4 Before Instruction After Instru...

Page 674: ...STFI Store Floating Point Value Interlocked 13 216 Note The STFI instruction is not interruptible because it completes when ready is signaled See Section 7 4 Interlocked Operations on page 7 13 ...

Page 675: ...on revision 6 0 or greater C32 silicon revision 2 0 or greater src1 register Rn1 0 n1 7 dst1 indirect disp 0 1 IR0 IR1 src2 register Rn2 0 n2 7 dst2 indirect disp 0 1 IR0 IR1 or any CPU register Opcode 31 24 23 16 8 7 0 15 1 1 0 0 0 0 0 0 0 src1 0 dst1 dst2 src2 Description Two STF instructions are executed in parallel Both src1 and src2 are assumed to be floating point numbers Cycles 1 Status Bit...

Page 676: ...0000 AR3 80 9835 AR3 80 9834 AR5 80 99D2 AR5 80 99D3 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 809835h 0 809835h 070C8000 8099D3h 0 8099D3h 0733C000 1 79750e 02 1 4050e 02 1 79750e 02 1 4050e 02 1 4050e 02 1 79750e 02 Note Cycle Count See subsection 8 5 2 Data Loads and Stores on page 8 24 for the effects of operand ordering on the cycle count ...

Page 677: ...to the dst memory location The src and dst oper ands are assumed to be signed integers Cycles 1 Status Bits LUF Unaffected LV Unaffected UF Unaffected N Unaffected Z Unaffected V Unaffected C Unaffected OVM Operation is not affected by OVM bit value Example STI R4 982Bh Before Instruction After Instruction R4 00 0004 2BD7 R4 00 0004 2BD7 DP 080 DP 080 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z ...

Page 678: ...F1 The src and dst operands are assumed to be signed integers Refer to Section 7 4 Interlocked Operations on page 7 13 for detailed information Cycles 1 Status Bits LUF Unaffected LV Unaffected UF Unaffected N Unaffected Z Unaffected V Unaffected C Unaffected OVM Operation is not affected by OVM bit value Example STII R1 98AEh Before Instruction After Instruction R1 00 0000 078D R1 00 0000 078D DP...

Page 679: ...ter C32 silicon revision 2 0 or greater src1 register Rn1 0 n1 7 dst1 indirect disp 0 1 IR0 IR1 src2 register Rn2 0 n2 7 dst2 indirect disp 0 1 IR0 IR1 or any CPU register Opcode 31 24 23 16 8 7 0 15 1 1 0 0 0 0 src2 dst2 dst1 1 src1 0 0 0 Description Two integer stores are performed in parallel If both stores are executed to the same address the value written is that of STI src2 dst2 Cycles 1 Sta...

Page 680: ...0 0035 R5 00 0000 0035 AR0 80 98D3 AR0 80 98D3 AR2 80 9830 AR2 80 9838 IR0 8 IR0 8 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 809838h 0 809838h 0DC 8098D3h 0 8098D3h 35 53 220 220 53 53 220 Note Cycle Count See subsection 8 5 2 Data Loads and Stores on page 8 24 for the effects of operand ordering on the cycle count ...

Page 681: ...e signed integers Cycles 1 Status Bits These condition flags are modified only if the destination register is R7 R0 LUF Unaffected LV 1 if an integer overflow occurs unchanged otherwise UF 0 N 1 if a negative result is generated 0 otherwise Z 1 if a 0 result is generated 0 otherwise V 1 if an integer overflow occurs 0 otherwise C 1 if a borrow occurs 0 otherwise OVM Operation is affected by OVM bi...

Page 682: ...ode 31 24 23 16 8 7 0 15 0 0 1 0 0 0 1 0 1 dst T src1 src2 Description The difference among the src1 and src2 operands and the C flag is loaded into the dst register The src1 src2 and dst operands are assumed to be signed integers Cycles 1 Status Bits These condition flags are modified only if the destination register is R7 R0 LUF Unaffected LV 1 if an integer overflow occurs unchanged otherwise U...

Page 683: ...n R0 00 0000 0000 R0 00 0000 0032 R5 00 0000 00C7 R5 00 0000 00C7 AR5 80 9800 AR5 80 9804 IR0 4 IR0 4 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 1 C 0 Data memory 809800h 0FA 809800h 0FA 250 50 199 199 250 Note Cycle Count See subsection 8 5 2 Data Loads and Stores on page 8 24 for the effects of operand ordering on the cycle count ...

Page 684: ...e subtraction If dst src is greater than or equal to 0 then dst src is left shifted one bit the least significant bit is set to 1 and the result is loaded into the dst register If dst src is less than 0 dst is left shifted one bit and loaded into the dst register The dst and src operands are assumed to be unsigned integers You can use SUBC to perform a single step of a multi bit integer division S...

Page 685: ... 00 0000 04F6 R1 00 0000 00C9 DP 080 DP 080 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 8098C5h 492 8098C5h 492 201 1170 1270 1170 Example 2 SUBC 3000 R0 3000 0BB8h Before Instruction After Instruction R0 00 0000 07D0 R0 00 0000 0FA0 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 4000 2000 ...

Page 686: ...e dst register The dst and src operands are assumed to be floating point num bers Cycles 1 Status Bits These condition flags are modified only if the destination register is R7 R0 LUF 1 if a floating point underflow occurs unchanged otherwise LV 1 if a floating point overflow occurs unchanged otherwise UF 1 if a floating point underflow occurs 0 otherwise N 1 if a negative result is generated 0 ot...

Page 687: ...e SUBF AR0 IR0 R5 Before Instruction After Instruction R5 07 33C0 0000 R5 05 1D00 0000 AR0 80 9888 AR0 80 9808 IR0 80 IR0 80 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 809888h 70C8000 809888h 70C8000 3 9250e 01 1 4050e 02 1 4050e 02 1 79750000e 02 ...

Page 688: ... T src1 src2 Description The difference between the src1 and src2 operands is loaded into the dst reg ister The src1 src2 and dst operands are assumed to be floating point num bers Cycles 1 Status Bits These condition flags are modified only if the destination register is R7 R0 LUF 1 if a floating point underflow occurs unchanged otherwise LV 1 if a floating point overflow occurs unchanged otherwi...

Page 689: ...0C8000 809888h 70C8000 809851h 733C000 809851h 733C000 3 9250e 01 1 4050e 02 1 4050e 02 1 79750e 02 1 79750e 02 Example 2 SUBF3 R7 R0 R6 Before Instruction After Instruction R0 03 4C20 0000 R0 03 4C20 0000 R6 00 0000 0000 R6 05 B7C8 0000 R7 05 7B40 0000 R7 05 7B40 0000 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 1 V 0 V 0 C 0 C 0 1 27578125e 01 6 281250e 01 5 00546875e 01 1 27578125e 01 6 281250...

Page 690: ... performed in parallel All registers are read at the beginning and loaded at the end of the execute cycle If one of the parallel operations STF reads from a register and the oper ation being performed in parallel SUBF3 writes to the same register STF ac cepts the contents of the register as input before it is modified by the SUBF3 If src3 and dst1 point to the same location src3 is read before the...

Page 691: ...3C0 0000 AR4 80 98B8 AR4 80 98B8 AR5 80 9850 AR5 80 9850 IR0 10 IR0 10 IR1 8 IR1 8 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 8098B0h 70C8000 8098B0h 70C8000 809860h 0 809860h 733C000 7 768750e 01 1 4050e 02 1 4050e 02 1 79750e 02 1 79750e 02 6 28125e 01 1 79750e 02 6 28125e 01 Note Cycle Count See subsection 8 5 2 Data Loads and Stores on page 8 24 for the effects...

Page 692: ...ds are assumed to be signed integers Cycles 1 Status Bits These condition flags are modified only if the destination register is R7 R0 LUF Unaffected LV 1 if an integer overflow occurs unchanged otherwise UF 0 N 1 if a negative result is generated 0 otherwise Z 1 if a 0 result is generated 0 otherwise V 1 if an integer overflow occurs 0 otherwise C 1 if a borrow occurs 0 otherwise OVM Operation is...

Page 693: ...0 n 27 Opcode 31 24 23 16 8 7 0 15 0 0 1 0 0 1 1 0 1 dst T src1 src2 Description The difference between the src1 operand and the src2 operand is loaded into the dst register The src1 src2 and dst operands are assumed to be signed integers Cycles 1 Status Bits These condition flags are modified only if the destination register is R7 R0 LUF Unaffected LV 1 if an integer overflow occurs unchanged oth...

Page 694: ...Z 0 V 0 V 0 C 0 C 0 50 2100 2150 2100 2150 Example 2 SUBI3 AR2 1 R4 R3 Before Instruction After Instruction R3 00 0000 0000 R3 00 0000 014A R4 00 0000 0226 R4 00 0000 0226 AR2 80 985E AR2 80 985E LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 80985Dh 0DC 80985Dh 0DC 220 550 330 550 220 Note Cycle Count See subsection 8 5 2 Data Loads and Stores on page 8 24 for the eff...

Page 695: ... An integer subtraction and an integer store are performed in parallel All regis ters are read at the beginning and loaded at the end of the execute cycle This means that if one of the parallel operations STI reads from a register and the operation being performed in parallel SUBI3 writes to the same register STI accepts the contents of the register as input before it is modified by the SUBI3 If s...

Page 696: ... 0035 R7 00 0000 0014 R7 00 0000 0014 AR2 80 982F AR2 80 982F AR7 80 983B AR7 80 983C IR0 10 IR0 10 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 80983Fh 0DC 80983Fh 0DC 80983Ch 0 80983Ch 35 53 200 53 220 20 20 220 53 Note Cycle Count See subsection 8 5 2 Data Loads and Stores on page 8 24 for the effects of operand ordering on the cycle count ...

Page 697: ...ds are assumed to be signed integers Cycles 1 Status Bits These condition flags are modified only if the destination register is R7 R0 LUF Unaffected LV 1 if an integer overflow occurs unchanged otherwise UF 0 N 1 if a negative result is generated 0 otherwise Z 1 if a 0 result is generated 0 otherwise V 1 if an integer overflow occurs 0 otherwise C 1 if a borrow occurs 0 otherwise OVM Operation is...

Page 698: ... modified only if the destination register is R7 R0 LUF 1 if a floating point underflow occurs unchanged otherwise LV 1 if a floating point overflow occurs unchanged otherwise UF 1 if a floating point underflow occurs 0 otherwise N 1 if a negative result is generated 0 otherwise Z 1 if a 0 result is generated 0 otherwise V 1 if a floating point overflow occurs 0 otherwise C Unaffected OVM Operatio...

Page 699: ...igned integers Cycles 1 Status Bits These condition flags are modified only if the destination register is R7 R0 LUF Unaffected LV 1 if an integer overflow occurs unchanged otherwise UF 0 N 1 if a negative result is generated 0 otherwise Z 1 if a 0 result is generated 0 otherwise V 1 if an integer overflow occurs 0 otherwise C 1 if a borrow occurs 0 otherwise OVM Operation is affected by OVM bit v...

Page 700: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description The SWI instruction performs an emulator interrupt This is a reserved instruc tion and should not be used in normal programming Cycles 4 Status Bits LUF Unaffected LV Unaffected UF Unaffected N Unaffected Z Unaffected V Unaffected C Unaffected OVM Operation is not affected by OVM bit value Mode Bit ...

Page 701: ... the specified trap vector N If the condition is not true ST GIE is set to its value before the TRAPcond instruction changes it The C3x provides 20 condition codes that can be used with this instruction see Table 13 12 on page 13 30 for a list of condition mnemonics condition codes and flags Condition flags are set on a previous instruction only when the destination register is one of the extended...

Page 702: ...ditionally 13 244 Example TRAPZ 16 Before Instruction After Instruction PC 0123 PC 0010 SP 809870 SP 809871 ST 0 ST 0 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory Trap V 16 10 809871h 124 ...

Page 703: ...dst G src Description The bitwise logical AND of the dst and src operands is formed but the result is not loaded in any register This allows for nondestructive compares The dst and src operands are assumed to be unsigned integers Cycles 1 Status Bits These condition flags are modified for all destination registers R27 R0 LUF Unaffected LV Unaffected UF 0 N MSB of the output Z 1 if a 0 output is ge...

Page 704: ...ample TSTB AR4 1 R5 Before Instruction After Instruction R5 00 0000 0898 R5 00 0000 0898 AR4 80 99C5 AR4 80 99C5 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 1 V 0 V 0 C 0 C 0 Data memory 8099C4h 767 8099C4h 767 2200 2200 1895 1895 ...

Page 705: ...1 1 1 T src1 0 0 0 0 0 src2 Description The bitwise logical AND between the src1 and src2 operands is formed but is not loaded into any register This allows for nondestructive compares The src1 and src2 operands are assumed to be unsigned integers Although this instruction has only two operands it is designated as a 3 operand instruction because operands are specified in the 3 operand format Cycle...

Page 706: ... memory 809885h 898 809885h 898 80992Dh 767 80992Dh 767 2200 2200 1895 1895 Example 2 TSTB3 R4 AR6 IR0 Before Instruction After Instruction R4 00 0000 FBC4 R4 00 0000 FBC4 AR6 80 99F8 AR6 80 99F0 IR0 8 IR0 8 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 8099F8h 1568 8099F8h 1568 Note Cycle Count See subsection 8 5 2 Data Loads and Stores on page 8 24 for the effects o...

Page 707: ...d dst operands is loaded into the dst register The dst and src operands are assumed to be unsigned integers Cycles 1 Status Bits These condition flags are modified only if the destination register is R7 R0 LUF Unaffected LV Unaffected UF 0 N MSB of the output Z 1 if a 0 output is generated 0 otherwise V 0 C Unaffected OVM Operation is not affected by OVM bit value Example XOR R1 R2 Before Instruct...

Page 708: ...0 IR1 1 1 indirect disp 0 1 IR0 IR1 dst register Rn 0 n 27 Opcode 31 24 23 16 8 7 0 15 0 0 1 0 1 0 0 0 0 dst T src1 src2 Description The bitwise exclusive OR between the src1 and src2 operands is loaded into the dst register The src1 src2 and dst operands are assumed to be unsigned integers Cycles 1 Status Bits These condition flags are modified only if the destination register is R7 R0 LUF Unaffe...

Page 709: ...UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 809800h 5AC3 809800h 5AC3 Example 2 XOR3 R5 AR1 1 R1 Before Instruction After Instruction R1 00 0000 0000 R1 00 0000 0F33 R5 00 000F FA32 R5 00 000F FA32 AR1 80 9826 AR1 80 9826 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 809825h 0FF5C1 809825h 0FF5C1 Note Cycle Count See subsection 8 5 2 Data Loads and Stores on...

Page 710: ...1 IR0 IR1 or any CPU register dst1 register Rn2 0 n2 7 src3 register Rn3 0 n3 7 dst2 indirect disp 0 1 IR0 IR1 Opcode 31 2423 16 8 7 0 15 1 1 1 0 1 1 dst 1 src1 dst2 src2 src3 Description A bitwise exclusive XOR and an integer store are performed in parallel All reg isters are read at the beginning and loaded at the end of the execute cycle If one of the parallel operations STI reads from a regist...

Page 711: ... affected by OVM bit value Example XOR3 AR1 R3 R3 STI R6 AR2 IR0 Before Instruction After Instruction R3 00 0000 0085 R3 00 0000 0000 R6 00 0000 00DC R6 00 0000 00DC AR1 80 987E AR1 80 987F AR2 80 98B4 AR2 80 98B4 IR0 8 IR0 8 LUF 0 LUF 0 LV 0 LV 0 UF 0 UF 0 N 0 N 0 Z 0 Z 0 V 0 V 0 C 0 C 0 Data memory 80987Eh 85 80987Eh 85 8098ACh 0 8098ACh 0DC 220 220 220 Note Cycle Count See subsection 8 5 2 Data...

Page 712: ... Chapter 13 Assembly Language Instructions Table A 1 along with the instruction descriptions fully defines the instruction words The opcodes are listed in numerical order Note that an undefined operation may occur if an illegal opcode is executed An Illegal opcode can only be generated by the misuse of the TMS320 floating point software tools by an error in the ROM code or by a defective RAM Appen...

Page 713: ... 0 0 0 0 0 1 1 1 CMPF 0 0 0 0 0 1 0 0 0 CMPI 0 0 0 0 0 1 0 0 1 FIX 0 0 0 0 0 1 0 1 0 FLOAT 0 0 0 0 0 1 0 1 1 IDLE 0 0 0 0 0 1 1 0 0 IDLE2 0 0 0 0 0 1 1 0 0 LDE 0 0 0 0 0 1 1 0 1 LDF 0 0 0 0 0 1 1 1 0 LDFI 0 0 0 0 0 1 1 1 1 LDI 0 0 0 0 1 0 0 0 0 LDII 0 0 0 0 1 0 0 0 1 LDM 0 0 0 0 1 0 0 1 0 LDP 0 0 0 0 1 0 0 0 0 LSH 0 0 0 0 1 0 0 1 1 LOPOWER 0 0 0 1 0 0 0 0 1 MAXSPEED 0 0 0 1 0 0 0 0 1 MPYF 0 0 0 0 ...

Page 714: ...0 1 1 1 0 0 POPF 0 0 0 0 1 1 1 0 1 PUSH 0 0 0 0 1 1 1 1 0 PUSHF 0 0 0 0 1 1 1 1 1 OR 0 0 0 1 0 0 0 0 0 RND 0 0 0 1 0 0 0 1 0 ROL 0 0 0 1 0 0 0 1 1 ROLC 0 0 0 1 0 0 1 0 0 ROR 0 0 0 1 0 0 1 0 1 RORC 0 0 0 1 0 0 1 1 0 RPTS 0 0 0 1 0 0 1 1 1 STF 0 0 0 1 0 1 0 0 0 STFI 0 0 0 1 0 1 0 0 1 STI 0 0 0 1 0 1 0 1 0 STII 0 0 0 1 0 1 0 1 1 SIGI 0 0 0 1 0 1 1 0 0 SUBB 0 0 0 1 0 1 1 0 1 SUBC 0 0 0 1 0 1 1 1 0 SUB...

Page 715: ... 0 0 0 1 ADDI3 0 0 1 0 0 0 0 1 0 AND3 0 0 1 0 0 0 0 1 1 ANDN3 0 0 1 0 0 0 1 0 0 ASH3 0 0 1 0 0 0 1 0 1 CMPF3 0 0 1 0 0 0 1 1 0 CMPI3 0 0 1 0 0 0 1 1 1 LSH3 0 0 1 0 0 1 0 0 0 MPYF3 0 0 1 0 0 1 0 0 1 MPYI3 0 0 1 0 0 1 0 1 0 OR3 0 0 1 0 0 1 0 1 1 SUBB3 0 0 1 0 0 1 1 0 0 SUBF3 0 0 1 0 0 1 1 0 1 SUB13 0 0 1 0 0 1 1 1 0 TSTB3 0 0 1 0 0 1 1 1 1 XOR3 0 0 1 0 1 0 0 0 0 LDFcond 0 1 0 0 LDIcond 0 1 0 1 BR D ...

Page 716: ...0 1 1 1 1 0 0 0 1 MPYF3 ADDF3 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 MPYF3 SUBF3 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 MPYI3 ADDI3 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 1 0 1 MPYI3 SUBI3 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 STF STF 1 1 0 0 0 0 0 STI STI 1 1 0 0 0 0 1 LDF LDF 1 1 0 0 0 1 0 LDI LDI 1 1 ...

Page 717: ...STI 1 1 0 1 0 1 0 FLOAT STF 1 1 0 1 0 1 1 LDF STF 1 1 0 1 1 0 0 LDI STI 1 1 0 1 1 0 1 LSH3 STI 1 1 0 1 1 1 0 MPYF3 STF 1 1 0 1 1 1 1 MPYI3 STI 1 1 1 0 0 0 0 NEGF STF 1 1 1 0 0 0 1 NEGI STI 1 1 1 0 0 1 0 NOT STI 1 1 1 0 0 1 1 OR3 STI 1 1 1 0 1 0 0 SUBF3 STF 1 1 1 0 1 0 1 SUBI3 STI 1 1 1 0 1 1 0 XOR3 STI 1 1 1 0 1 1 1 Reserved for reset traps and interrupts 0 1 1 1 1 1 1 1 1 The opcode is the same f...

Page 718: ...B 1 Appendix A TMS320C31 Boot Loader Source Code This appendix contains the source code for the C31 boot loader Appendix B ...

Page 719: ... LOCAL MEMORY REGISTER THE PROGRAM BLOCKS FOLLOW THE FIRST TWO WORDS OF EACH PROGRAM BLOCK CONTAIN THE BLOCK SIZE AND MEMORY ADDRESS TO BE LOADED INTO WHEN THE ZERO BLOCK SIZE IS READ THE PROGRAM BLOCK LOADING IS TERMINATED THE PC WILL BRANCH TO THE STARTING ADDRESS OF THE FIRST PROGRAM BLOCK 3 IF SERIAL PORT 0 IS SELECTED FOR BOOT LOADING THE PROCESSOR WILL WAIT FOR THE INTERRUPT FROM THE RECEIVE...

Page 720: ...h dint word 809FCBh word 809FCCh word 809FCDh word 809FCEh word 809FCFh word 809FD0h word 809FD1h word 809FD2h word 809FD3h word 809FD4h word 809FD5h word 809FD6h word 809FD7h word 809FD8h word 809FD9h word 809FDAh word 809FDBh word 809FDCh word 809FDDh word 809FDEh word 809FDFh trap0 word 809FE0h trap1 word 809FE1h trap2 word 809FE2h trap3 word 809FE3h trap4 word 809FE4h trap5 word 809FE5h trap6 ...

Page 721: ...addr 808000h LDI 404Ch SP initialize stack pointer to LSH 9 SP ram0 addr 809800h LDI 0 R0 set start address flag off intloop TSTB 8 IF test for ext int3 BNZ serial on int3 go to serial LDI 8 AR1 load 001000h 2 9 AR1 TSTB 1 IF test for int0 BNZ eprom_load branch to eprom_load if int0 1 LDI 2000h AR1 load 400000h 2 9 AR1 TSTB 2 IF test for int1 BNZ eprom_load branch to eprom_load if int1 1 LDI 7FF8h...

Page 722: ...LLU AR3 load new word according to mem width LDI R1 AR4 set destination address LDI R0 R0 test start address loaded flag LDIZ R1 AR2 load start address if flag off LDI 1 R0 set start dest address flag on SUBI 1 AR3 sub address with loop CALLUAR3 load new word according to mem width LDI 1 R0 set dest address flag off ADDI 1 AR3 sub address without loop BR load2 jump to load a new block when loop co...

Page 723: ... return from subroutine space 26 loop_w RPTB load_w PGM load loop sub_w LDI AR1 1 R1 read a new 32 bit word LDI R0 R0 test load address flag BNN end_w load_w STI R1 AR4 1 store new word to dest address end_w RETSU return from subroutine space 14 loop_b RPTB load_b PGM load loop sub_b LDI AR1 1 R1 AND 0FFh R1 load 1st byte LSB LDI AR1 1 R2 AND 0FFh R2 LSH 8 R2 OR R2 R1 load 2nd byte LDI AR1 1 R2 AN...

Page 724: ...ader Source Code This appendix includes a description of the C32 boot loader sequence of events and a listing of its source code Topic Page C 1 Boot Loader Source Code Description C 2 C 2 Boot Loader Source Code Listing C 4 Appendix C ...

Page 725: ...ol register values of the source program These values are temporarily saved in the DMA source address register DMA destination ad dress register and DMA transfer counter registers respectively Then the program reads the block size with the read_mc routine If the block size is 0 the boot loader restores the values of IOSTRB STRB0 and STRB1 previously saved and branches to the destination address of...

Page 726: ...ock size RC Memory control word read routine AR0 Memory width R5 Process interrupts INT0 INT1 INT2 Process memory width word Read and store strobe values Select read routine Interrupt flag IF Block size 0 Transfer one block of data or program Memory block read routine AR1 Memory width R5 Boot source address AR3 Handshake mode IOF Read destination address Read destination strobe Read block size Boo...

Page 727: ...w The C32 will continuously toggle the IACK signal while waiting for the host to assert data ready signal pin XF1 2 The boot operation involves transfer of one or more source blocks from the boot media to the destination memory The block structure of the boot table serves the purpose of distributing the source data program among different memory spaces Each block is preceded by several 32 bit cont...

Page 728: ... of the first block and start program execution from that location C32 boot loader program register assignments and altered mem locations AR7 peripheral memory map IOF XF0 handshake O AR0 read cntrl data subr pointer IOF XF1 handshake I AR1 read block data prg subr pointer R2 read STRB value R4 write STRB value AR2 read STRB pointer AR4 write STRB pointer AR3 read data prg pointer AR5 write data p...

Page 729: ...8 AR3 001000h 2 9 BNZ exit3 ADDI 4 AR2 808068h STRB1 AR2 TSTB 4 R0 test for INT2 LDINZ 4800h AR3 900000h 2 9 BZ wait1 exit3 TSTB 8 R0 test 1 INT3 asserted BZ exit2 test 2 INXF1 low not used TSTB 80h IOF enable handshake mode if LDI 6 IOF test 1 passed exit2 LDI 0Fh R2 LSH 16 R2 force boot data size to 32 OR AR2 R2 force boot mem width to 32 STI R2 AR2 LSH 9 AR3 boot mem start addr AR3 xx000001 1 b...

Page 730: ...Z label2 no go around LDI AR7 4 R0 DMA src STI R0 AR7 60h restore IOSTRB LDI AR7 6 R0 DMA dst STI R0 AR7 64h restore STRB0 LDI AR7 8 R0 DMA cnt STI R0 AR7 68h restore STRB1 BU IR1 branch to start of program label2 LDI R1 RC setup transfer loop SUBI 1 RC RC 1 RC Process block destination address save start address of first block CALLU AR0 read boot memory cntrl word LDI R1 AR5 set dest addr AR5 CMP...

Page 731: ...R4 AR4 set write strobe NOP pipeline loop4 STI R1 AR5 write data prg BU block process next block Load R5 with 0 load read_s0 to AR0 and initialize serial port_0 serial LDI read_s0 AR0 use serial to read cntrl words LDI 0 R5 memory WIDTH serial LDI 0 R dummy LDI AR7 AR2 dummy LDI 111h R0 0000111h R0 STI R0 AR7 43h set CLKR DR FSR as serial LDI 0A30h R7 port pins LSH 16 R7 A300000h R7 STI R7 AR7 40h...

Page 732: ...ccumulator loop1 ADDI 3 SP 808027h SP CALLU read_m read memory once R6 SUBI 3 SP 808024h SP AND3 R6 BK R7 apply mask LSH R0 R7 shift OR R7 R1 accumulate R1 ADDI R5 R0 increment shift value DBU AR6 loop1 decrement of chunks AR6 RETSU Perform a single memory read from the source boot table Handshake enabled if IOXF0 bit of IOF reg is set disabled when reset IACK will pulse continuously if handshake ...

Page 733: ...ader Source Code Listing C 10 LDI 2 IOF assert data acknowledge XF0 low to host loop6 TSTB 80h IOF wait for data not ready BZ loop6 XF1 high from host LDI 6 IOF deassert data acknowledge XF0 high to host RETSU ...

Page 734: ...gital signal ARAU Auxiliary register arithmetic unit A 32 bit ALU used to calculate indi rect addresses using the auxiliary registers as inputs and outputs arithmetic logic unit ALU The part of the CPU that performs arithmetic and logic operations auxiliary registers ARn A set of registers used primarily in address gen eration auxiliary register arithmetic unit ARAU Auxiliary register arithmetic u...

Page 735: ... product register temporary register hardware stack and auxiliary registers etc when the device enters exits a subroutine such as an interrupt service routine CPU Central processing unit The unit that coordinates the functions of a processor CPU cycle The time it takes the CPU to go through one logic phase during which internal values are changed and one latch phase during which the values are hel...

Page 736: ...nded precision floating point format A 40 bit representation of a floating point number with a 32 bit mantissa and an 8 bit exponent extended precision register A 40 bit register used primarily for extended precision floating point calculations Floating point operations use bits 39 0 of an extended precision register Integer operations however use only bits 31 0 F FIFO buffer First in first out bu...

Page 737: ...DMA responds to interrupts from exter nal interrupt pins the serial ports the timers and the DMA coprocessor interrupt A signal sent to the CPU that when not masked forces the CPU into an ISR This signal can be triggered by an external device an on chip peripheral or an instruction TRAP for example interrupt acknowledge IACK A signal indicating that an interrupt has been received and that the prog...

Page 738: ...s of floating point operations per second A measure of floating point processor speed that counts of the number of floating point operations made per second Also called megaflops microcomputer mode A mode in which the on chip ROM boot loader is enabled This mode is selected via the MP MCBL pin microprocessor mode A mode in which the on chip ROM is disabled This mode is selected via the MP MCBL pin...

Page 739: ...ol signal that indicates the direction of transfer when communicating to an external device register file A bank of registers repeat counter RC register A 32 bit register in the CPU register file that specifies the number of times to repeat a block of code when performing a block repeat repeat mode A zero overhead method for repeating the execution of a block of code Using repeat modes allows time...

Page 740: ... point number with a 24 bit mantissa and an 8 bit exponent single precision integer format A 2s complement 32 bit format for inte ger data single precision unsigned integer format A 32 bit unsigned format for integer data software interrupt An interrupt caused by the execution of a TRAP instruc tion ST See status register stack A block of memory reserved for storing and retrieving data on a first ...

Page 741: ...ed number of wait states for a given off chip memory space lower program upper program data or I O X XA0 XA13 External address pins for data program memory or I O devices These pins are on the expansion bus of the C30 See also A0 A23 XD0 XD31 External data bus pins that transfer data between the processor and external data program memory or I O devices of the C30 See also D0 D31 Z zero fill The pr...

Page 742: ...te value of floating point instruction ABSF 13 41 integer instruction ABSI 13 44 add floating point value instruction ADDF 13 51 3 operand instruction 13 53 integer ADDI 13 57 3 operand instruction 13 58 with carry instruction ADDC 13 48 3 operand instruction 13 49 address definition D 1 address pins external D 8 addressing 6 1 6 32 modes 3 operand 2 17 13 24 13 25 branch 2 17 definition D 1 gener...

Page 743: ...13 67 13 68 complement NOT 13 184 13 185 OR 13 188 13 189 branch conditionally delayed BcondD 13 81 13 82 standard Bcond 13 79 13 80 assembly language instructions continued unconditionally delayed BRD 13 84 standard BR 13 83 call subroutine CALL 13 85 conditionally CALLcond 13 86 13 87 categories 2 operand 13 3 3 operand 13 4 interlocked operation 13 5 13 6 load and store 13 2 low power control 1...

Page 744: ...on RPTS 13 211 13 212 restore clock to regular speed MAXSPEED 13 145 return from interrupt conditionally RETI cond 13 198 13 199 from subroutine conditionally RETS cond 13 200 13 201 assembly language instructions continued rotate left ROL 13 204 assembly language instructions continued left through carry ROLC 13 205 13 206 right ROR 13 207 right through carry RORC 13 208 round floating point valu...

Page 745: ...rt 11 6 TMS320C32 11 14 11 24 data stream 11 20 description 11 14 external memory interface 11 23 mode selection 11 14 mode selection flowchart 11 17 sequence 11 15 serial port load flowchart 11 18 branch addressing modes 2 17 conditionally delayed instruction BcondD 13 81 standard instruction Bcond 13 79 conflicts 8 4 delayed 7 9 7 10 execution 7 10 incorrect use of 7 9 incorrectly placed 7 7 7 1...

Page 746: ...ction 7 40 latency 7 35 CPU continued processing block diagram 7 34 processing cycle 7 33 primary registers 2 9 register file 3 2 registers 3 1 3 20 auxiliary AR7 AR0 2 10 3 4 block size BK 2 11 3 4 block repeat RS RE 3 17 data page pointer DP 2 10 3 4 extended precision R7 R0 2 10 3 3 I O flag IOF 2 11 3 16 index IR1 IR0 2 10 3 4 interrupt flag IF 2 11 3 11 7 32 bits defined 3 13 interrupt enable...

Page 747: ...sic operation 12 50 block diagram 2 25 channel synchronization 12 65 12 67 DMA continued functional description 12 48 global control register 12 53 internal priority schemes for C32 12 62 interrupts 12 64 priorities 12 62 register 12 51 transfer counter register 12 58 coprocessor definition D 3 destination register 12 67 12 68 destination source address regis ter 12 57 12 59 Initialization reconfi...

Page 748: ... FIX instruction 5 41 flowchart 5 42 fixed data rate timing operation 12 36 burst mode timing 12 36 continuous mode timing 12 36 fixed priority for C32 12 62 flag carry 13 29 condition floating point underflow 13 29 latched floating point underflow 13 29 latched overflow 13 29 negative 13 29 overflow 13 29 zero 13 29 FLOAT instruction flowchart 5 43 floating point addition flowchart 5 33 multiplic...

Page 749: ...ddressing mode 13 25 ARAUs 6 5 auxiliary register 6 5 parallel addressing mode 13 26 with postdisplacement 6 11 with postinde 6 15 6 18 with predisplacement 6 9 6 11 indirect addressing continued with preinde 6 13 6 15 instruction 2 operand 13 3 3 operand 13 4 cache 4 19 algorithm 4 21 TMS320C32 2 16 CALL 7 11 CALLcond 7 11 DBR 8 8 FIX 5 41 FLOAT 5 43 IACK 7 35 IDLE2 7 49 interlocked operations 13...

Page 750: ... 7 35 block diagram 7 34 7 39 serial port 12 34 receive timer 12 34 transmit timer 12 34 interrupt continued service routine ISR 7 35 7 50 instruction 7 35 timer 12 2 12 13 vector table TMS320C30 and TMS320C31 7 26 7 28 TMS320C32 7 29 7 30 interrupt and trap branch instructions TMS320C31 microcomputer mode 4 17 vector locations TMS320C32 4 18 7 30 interrupt service routine ISR definition D 4 inter...

Page 751: ...ignals 9 3 maps peripheral bus TMS320C30 4 9 TMS320C31 4 11 memory continued TMS320C32 4 12 TMS320C30 4 2 4 4 TMS320C31 4 6 microcomputer mode TMS320C30 4 3 TMS320C31 4 5 TMS320C32 4 7 microprocessor mode TMS320C30 4 2 TMS320C31 4 5 TMS320C32 4 7 organization block diagram TMS320C30 2 14 TMS320C31 2 15 TMS320C32 2 16 parallel multiplies and adds 8 30 stores 8 29 pipeline conflicts 8 8 program TMS3...

Page 752: ... 13 17 13 19 multiplies and adds instruction word for mat 8 30 parallel Instructions ADDI3 and STI 13 60 13 61 FIX and STI 13 101 13 102 parallel instructions ABSF and STF 13 42 13 43 ABSI and STI 13 46 13 47 ADDF3 and STF 13 55 13 56 ASH3 and STI 13 76 13 78 FLOAT and STF 13 105 13 106 LDF and LDF 13 119 13 120 LDF and STF 13 121 LDI and LDI 13 129 13 130 LDI and STI 13 131 13 132 LSH3 and STI 13...

Page 753: ...onflicts 8 4 branch 8 4 memory 8 8 8 9 register 8 6 resolving memory 8 22 decode unit 8 2 definition D 6 execute unit 8 2 fetch unit 8 2 memory accesses 8 24 pipeline continued operation 7 42 introduction 8 1 read unit 8 2 structure 8 2 major units 8 2 POP floating point value instruction POPF 13 195 integer instruction 13 194 power management modes 7 49 7 52 IDLE2 7 49 7 51 primary bus 9 2 bus cy...

Page 754: ...data page pointer DP 2 10 3 4 extended precision R7 R0 2 10 3 3 condition flags 13 39 extended precision registers R7 R0 7 9 I O flag IOF 2 11 3 16 index IR1 IR0 2 10 3 4 interrupt flag IF 2 11 3 11 asynchronous accesses 7 45 interrupt trap table pointer ITTP bit 3 14 interrupt enable IE 2 11 3 9 12 59 12 62 repeat end address RE 7 2 repeat start address RS 7 2 repeat counter RC 2 11 3 17 7 2 stat...

Page 755: ...11 from subroutine conditionally RETS cond 13 200 from subroutine conditionally instruction RETS cond 7 11 RND instruction 5 39 flowchart 5 40 ROM See memory rotate left instruction ROL 13 204 left through carry ROLC 13 205 right instruction ROR 13 207 right through carry instruction RORC 13 208 rotating priority for C32 12 63 round floating point value instruction RND 13 202 rounding of floating ...

Page 756: ...nterrupt enable GIE bit C30 interrupt considerations 7 44 C3x interrupt considerations 7 41 STFI instruction 7 14 STII instruction 7 14 store floating point value STF 13 214 interlocked STFI 13 215 integer instruction STI 13 219 interlocked STII 13 220 STRB signal 9 3 9 15 STRB0 control register 10 8 STRB1 control register 10 8 subtract floating point value instruction SUBF 13 228 integer SUBI 13 ...

Page 757: ...ry external widths 2 20 memory organization block diagram 2 16 program memory 2 19 serial ports 12 15 short floating point format 5 4 5 6 timers 12 2 trap vector locations 7 30 TMS320C3x device differences 2 27 devices 1 2 compared 1 5 DSPs introduction 1 1 functional block diagram 1 3 TMS320C3x continued key specifications 1 3 serial port interface examples 12 41 12 48 TMS320LC31 power management...

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