TMS320C32 Memory Overview
10-3
TMS320C32 Enhanced External Memory Interface
10.2 TMS320C32 Memory Overview
The following sections describe examples, control register setups, and
restrictions necessary to fully understand the operation and functionality of the
external memory interface.
10.2.1 External Memory Interface Overview
The ’C32 memory interface accesses external memory through one 24-bit
address and one 32-bit data bus that is shared by three mutually-exclusive
strobes (STRB0, STRB1, and IOSTRB). Depending on the address accessed,
the ’C32 activates one of these strobes according to the memory map shown
in Figure 4–3 on page 4-8.
STRB0 and STRB1 can access 8-, 16-, or 32-bit data from 8-, 16-, or 32-bit
wide memory. This is accomplished by four signals in each strobe:
STRBx_B3/A
–1
, STRBx_B2/A
–2
, STRBxB1, and STRBx_B0. These signals
serve as byte-enable pins to access one byte, half word, or a full word from the
external memory. The first two signals also serve as additional address pins
to perform two or four consecutive accesses in 8-bit or 16-bit-wide external
memory. The ’C32 controls the behavior of these pins through the data size
and memory width bit fields in the corresponding strobe control register, as
follows:
-
Memory width (default value dependent on PRGW pin level)
J
8-bit-wide memory
H
STRBx_B3/A
–1
and STRBx_B2/A
–2
as address pins
H
STRBx_B0 as byte-enable/chip-select signal
H
STRBx_B1 unused
J
16-bit-wide memory
H
STRBx_B3/A
–1
as address pin
H
STRBx_B1 and STRBx_B0 as byte-enable signal
H
STRBx_B2 unused
J
32-bit-wide memory
H
STRBx_B3, STRBx_B2, STRBx_B1, and STRBx_B0 as byte-
enable signals
-
Data size
J
8-bit data, physical address = logical address shift right by 2
J
16-bit data, physical address = logical address shift right by 1
J
32-bit data, physical address = logical address
