Timers
12-6
Table 12–1. Timer Global-Control Register Bits Summary (Continued)
Abbreviation
Description
Name
Reset
Value
C/P
0
Clock/pulse
mode control
When C/P = 1, clock mode is chosen, and the signal-
ing of the TSTAT flag and external output has a 50%
duty cycle.
When C/P = 0, the status flag and external output
will be active for one H1 cycle during each timer
period (see Figure 12–4 on page 12-8).
CLKSRC
0
Clock source
This bit specifies the source of the timer clock.
When CLKSRC = 1, an internal clock with a frequen-
cy equal to one-half of the H1 frequency is used to
increment the counter. The INV bit has no effect on
the internal clock source.
When CLKSRC = 0, you can use an external signal
from the TCLK pin to increment the counter. The ex-
ternal clock is synchronized internally, thus allowing
external asynchronous clock sources that do not ex-
ceed the specified maximum allowable external
clock frequency. This is less than f(H1)/2.
See section 12.1.6,
Timer Operation Modes, on
page 12-10 for a description of the relationship be-
tween FUNC and CLKSRC.
INV
0
Inverter control
bit
If an external clock source is used and INV = 1, the
external clock is inverted as it goes into the counter.
If the output of the pulse generator is routed to TCLK
and INV = 1, the output is inverted before it goes to
TCLK (see Figure 12–1 on page 12-2).
If INV = 0, no inversion is performed on the input or
output of the timer. The INV bit has no effect, regard-
less of its value, when TCLK is used in I/O port
mode.
TSTAT
0
Timer status bit
This bit indicates the status of the timer. It tracks the
output of the uninverted TCLK pin. This flag sets a
CPU interrupt on a transition from 0 to 1. A write has
no effect.
† x = 0 or 1 (set to value read on TCLK)
