DMA Controller
12-53
Peripherals
12.3.3.1 DMA Global-Control Register
The global-control register controls the state in which the DMA controller
operates. This register also indicates the status of the DMA, which changes
every cycle. Source and destination addresses can be incremented, decrem-
ented, or synchronized using specified global-control register bits. At system
reset, all bits in the DMA control register are cleared to 0. Figure 12–36 shows
the global-control registers for the ’C30 and ’C31 devices. Figure 12–37 and
Figure 12–38 show the global-control registers for the ’C32. Table 12–6 shows
the register bits, bit names, and bit functions.
Figure 12–36. TMS320C30 and TMS320C31 DMA Global-Control Register
DECSRC
DECDST
31
xx
TCINT
TC
INCDST
15 14
12
11
10
9
8
7
6
5
4
3
2
1
0
INCSRC
START
R/W
R/W
R/W
R/W
R/W
R
R/W
xx
R/W
SYNC
STAT
R/W
Notes:
1) R = read, W = write
2) xx = reserved bit, read as 0
Figure 12–37. TMS320C32 DMA0 Global-Control Register
PRIORITY
MODE
DMAO
PRI
DECSRC
DECDST
31
TCINT
TC
INCDST
15
13
12
11
10
9
8
7
6
5
4
3
2
1
0
INCSRC
START
R/W
R/W
R/W
R/W
R/W
R
R/W
xx
R/W
SYNC
STAT
R/W
14
R/W
R/W
Notes:
1) R = read, W = write
2) xx = reserved bit, read as 0
Figure 12–38. TMS320C32 DMA1 Global-Control Register
xx
DMA1
PRI
DECSRC
DECDST
31
TCINT
TC
INCDST
15
13
12
11
10
9
8
7
6
5
4
3
2
1
0
INCSRC
START
R/W
R/W
R/W
R/W
R/W
R
R/W
xx
R/W
SYNC
STAT
R/W
14
R/W
Notes:
1) R = read, W = write
2) xx = reserved bit, read as 0
