Direct Memory Access (DMA)
2-24
2.10 Direct Memory Access (DMA)
The on-chip DMA controller can read from or write to any location in the
memory map without interfering with the CPU operation. The ’C3x can inter-
face to slow, external memories and peripherals without reducing throughput
to the CPU. The DMA controller contains its own address generators, source
and destination registers, and transfer counter. Dedicated DMA address and
data buses minimize conflicts between the CPU and the DMA controller. A
DMA operation consists of a block or single-word transfer to or from memory.
See Section 12.3,
DMA Controller, on page 12-48 for more information.
Figure 2–10 shows the DMA controller and its associated buses.
The ’C30 and ’C31 DMA coprocessors have one channel, while the ’C32 DMA
coprocessor has two channels. Each channel of the ’C32 DMA coprocessor is
equivalent to the ’C30/31 DMA with the addition of user-configurable priorities.
Because the DMA and CPU have distinct buses on the ’C3x devices, they can
operate independently of each other. However, when the CPU and DMA access
the same on-chip or external resources, the bandwidth can be exceeded and
priorities must be established. The ’C30 and ’C31 assign highest priority to the
CPU. The ’C32 DMA coprocessor provides more flexibility by allowing you to
choose one of the following priorities:
-
CPU:
For all resource conflicts, the CPU has priority over the DMA.
-
DMA:
For all resource conflicts, the DMA has priority over the CPU.
-
Rotating: When the CPU and DMA have a resource conflict during con-
secutive instruction cycles, the CPU is granted priority. On the following
cycle, the DMA is granted priority. Alternate access continues as long as
the CPU and DMA requests conflict in consecutive instruction cycles.
The DMA/CPU priority is configured by the DMA PRI bit fields of the corresponding
DMA global-control register. See Section 12.3,
DMA Controller, on page 12-48 for
a complete description.
