Interrupts
5-28
Note:
The INTR instruction does not affect IFR flags. When you use the INTR
instruction to initiate an interrupt that has an associated flag bit in the IFR,
the instruction neither sets nor clears the flag bit. No software write operation
can set the IFR flag bits; only the appropriate hardware requests can. If a
hardware request has set the flag for an interrupt and then the INTR instruc-
tion is used to initiate that interrupt, the INTR instruction will not clear the flag.
-
NMI. This instruction forces a branch to interrupt vector location 24h, the
same location used for the nonmaskable hardware interrupt NMI. Thus,
you can either initiate NMI by driving the NMI pin low or by executing an
NMI instruction. When the NMI instruction is executed, INTM is set to 1 to
disable maskable interrupts.
-
TRAP. This instruction forces the CPU to branch to interrupt vector loca-
tion 22h. The TRAP instruction does
not disable maskable interrupts
(INTM is not set to 1); thus when the CPU branches to the interrupt service
routine, that routine can be interrupted by the maskable hardware inter-
rupts (in addition to RS and NMI).
If the INTM bit is set to 1 during the acknowledgement process, all hardware-
initiated maskable interrupts are disabled and, thus, cannot interfere with the
interrupt service routine.
To determine which vector address has been assigned to each of the interrupts
on a specific ’C2xx device, see subsection 5.6.2 (on page 5-16). Interrupt vec-
tor locations are spaced apart by two addresses so that a 2-word branch
instruction can be accommodated in each location.
Figure 5–10 summarizes how nonmaskable interrupts are handled by the
CPU.
