Interrupts
5-18
5.6.3
Maskable Interrupts
When a maskable interrupt is successfully requested by a hardware device or
by an external pin, the corresponding flag or flags are activated. These flags
are activated whether or not the interrupt is later acknowledged by the proces-
sor.
Two registers on the ’C2xx contain flag bits:
-
Interrupt flag register (IFR), a 16-bit, memory-mapped register located at
address 0006h in data-memory space.The IFR is explained in detail in
subsection 5.6.4
-
Interrupt control register (ICR), a 16-bit register located at address FFECh
in I/O space.The ICR is explained in subsection 5.6.6.
The IFR contains flag bits for all the maskable interrupts. The ICR contains
additional flag bits for the interrupts INT2 and INT3. For all maskable interrupts
except INT2 and INT3, an interrupt request is sent to the CPU as soon as the
interrupt signal is sent by the pin or on-chip peripheral. For INT2 or INT3, the
interrupt request is only sent to the CPU if the interrupt signal is not masked
by its mask bit in the ICR. Figure 5–5 shows the process for successfully re-
questing INT2 or INT3.
Figure 5–5. INT2/INT3 Request Flow Chart
Interrupt request sent to CPU
Interrupt unmasked
in ICR?
Yes
No
Corresponding ICR flag bit set
INT2 or INT3 asserted at pin
