Test Results
56
JAJU324B – March 2015 – Revised July 2017
翻訳版
—
最新の英語版資料
http://www-s.ti.com/sc/techlit/TIDU832
Copyright © 2015–2017, Texas Instruments Incorporated
EMI/EMC
規格準拠、産業用温度範囲のデュアルポート・ギガビット・イーサネットの
リファレンス・デザイン
5.2.3
PMIC for Sitara AM3359 Host Processor
The TPS65910A3 output voltages were verified and compared against the expected voltages based on
the TPS65910A3 EEPROM pin configuration.
表
表
23. Measured Voltages on the PMIC TPS65910A3
SIGNAL
EXPECTED VOLTAGE
MEASURED VOLTAGE
VIO
1.5 V
1.52 V
VDD1
1.1 V
1.11 V
VDD2
1.1 V
1.11 V
VDD3
OFF
N/A
VDIG1
1.8 V
NC. VDIG1 pin was not connected in this design.
VDIG2
1.8 V
1.81 V
VPLL
1.8 V
1.82 V
VDAC
1.8 V
1.80 V
VAUX1
1.8 V
1.82 V
VAUX2
3.3 V
3.31 V
VAUX33
3.3 V
3.33 V
VMMC
3.3 V
3.32 V
VRTC
OFF
N/A
The sequencing has not been tested. Please see
TPS65910Ax User's Guide For AM335x Processors
for
further details
