Texas Instruments TIDA-00204, Manual

Page: 31 / 86

XI CLK_OUT
XO
XI
XO CLK_OUT
C
X
C
Y
2
5
MH
z
25 MHz
DP83867IR (PHY 1) DP83867IR (PHY 2)
X Y L S
C C 2 (C C )
= = ´ -
www.tij.co.jp
System Overview
31 JAJU324B – March 2015 – Revised July 2017
TIDU832
翻訳版
—
最新の英語版資料
http://www-s.ti.com/sc/techlit/TIDU832
Copyright © 2015–2017, Texas Instruments Incorporated
EMI/EMC
規格準拠、産業用温度範囲のデュアルポート・ギガビット・イーサネットの
リファレンス・デザイン
2.3.1.4 System Clocks
There are several options to apply the clocks. For systems with distributed clocks, a clock distribution
circuit can be used too. The initial design leverages a crystal on each DP83867IR as well as on AM3359
Sitara. This was due to initial test and debug to allow individual component testing.
2.3.1.4.1 Individual Crystals
The crystal manufacturers define the load capacitance of their crystal in their data sheet. This load
capacitance C
L
is the sum of the PCB parasitic stray capacitance C
S
and the external load capacitors C
X
and C
Y
, respectively, as per
式
14 . Assuming that the external load capacitors are the same value, they
can be calculated with
式
14 .
(14)
C
S
is the stray capacitance (device and PCB) this value can be assumed to a few pF as a rule of thumb.
The load capacitors need to be NPO/COG type.
表
17 shows the selected load capacitors per crystal and
per device on the TIDA-00204.
表 表
17. Parallel Capacitors Needed for Oscillation Circuit
CRYSTAL DEVICE C
L
C
S
C
X
= C
Y
ABM3-25.000MHZ-D2W-T DP83867IR 18 pF 4 pF 27 pF
ABM3-24.000MHZ-D2W-T AM3359 18 pF 4 pF 27 pF
ABM3-12.000MHZ-D2Y-T FT2232HL 18 pF 4 pF 27 pF
MC-306 32.7680K-A0:ROHS AM3359 (RTC) 12.5 pF 3 pF 19 pF
In this design, the default configuration is one crystal at each DP83867IR PHY. However, the hardware is
prepared thanks to 0- Ω resistors to clock the second DP83867IR PHY from the PHY 1, as shown in
図
16 .
If desired, this configuration can be tested.
図 図
16. Crystal Configuration for DP83876IR and Option to Clock the Second DP83867IR PHY From the
First DP83867IR