System Overview
7
JAJU324B – March 2015 – Revised July 2017
翻訳版
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最新の英語版資料
http://www-s.ti.com/sc/techlit/TIDU832
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2.2.2.2
Medium Independent Interface: MAC Layer Interface
For the MAC layer interface to the Gigabit PHY, there are three different options defined in the IEEE
802.3ab standard: The standard Media Independent Interface (MII), the GMII, SGMII, or the RGMII.
2.2.2.2.1
GMII
The purpose of GMII is to make various physical media transparent to the MAC layer. The GMII accepts
either GMII or MII data, control, and status signals and routes them either to the 1000BASE-T, 100BASE-
TX, or 10BASE-T modules, respectively.
The GMII provides full-duplex operation and is an 8-bit wide transmit and receive data path interface
clocked at 125 MHz defining speeds up to 1000 Mb/s. GMII is backwards compatible with the MII
specification, thereby supporting 10 (2.5 MHz) and 100 (25 MHz) Mb/s speeds. Data and delimiters are
synchronous to clock references. It also provides a simple management interface.
The transmit signals are GTX_CLK, TX_CLK, TX_D[7:0], TX_EN, and TX_ER. The GTX_CLK signal is
supplied to the PHY when it is operating in Gigabit mode. When this is done, the TX_D, TX_EN, and
TX_ER are synchronized to the GTX_CLK signal. For a 10/100-Mb operation, the TX_CLK is supplied to
the MAC, and the TX_CLK signal is used to synchronize the signals (TX_D, TX_EN, and TX_ER). The
receiver signals are RX_CLK, RX_D[7:0], RX_DV, RX_ER, COL, and CS. The GMII uses in total a
maximum of 25 pins.
2.2.2.2.2
RGMII
The RGMII is designed to reduce the number of pins required to interconnect the MAC and PHY (12 pins
for RGMII relative to 24 pins for GMII). With this optimization, the RGMII consists of 12 signals: 6 signals
for receive, which are RX_CTL, RX_CLK, RX_D[3:0], and 6 for transmit, which are TX_CTL,
TX_CLK,TX_D[3:0]. To accomplish this, the data paths and all associated control signals are reduced and
are multiplexed. Both rising and trailing edges of the clock are used. The TX_CTL and RX_CTL signal
carries data valid (
DV
) on the rising edge and
DV XOR ERROR
on the falling edge, for CTL signals there
is no change between 10/100Mb/s or 1000Mb/s operation.
For a Gigabit operation, the GTX_CLK and RX_CLK clocks are 125 MHz, and for 10- and 100-Mb/s
operation, the clock frequencies are 2.5 MHz and 25 MHz, respectively.
2.2.2.2.3
SGMII
The SGMII differs from the GMII and RGMII by having a higher clock frequency and the 8b/10b (SerDes)
coded interface. It uses differential pairs at a 625-MHz clock frequency double data rate (DDR) for TX and
RX data and for TX and RX clock. The transmit and receive path uses one differential pair for data and in
some cases one for clock. TX and RX clocks must be generated on device output but are optional on
device input. With revision 1.8 of the SGMII standard, clock recovery can be used, removing the need for
the clock signal. This means that the SGMII can be a 4- to 8-pin solution.
