Terasic DE0-CV, User Manual

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DE0-CV User Manual
30
www.terasic.com
May 4, 2015
GPIO_1_D18 PIN_J13 GPIO Connection 1[18]
GPIO_1_D19 PIN_L8 GPIO Connection 1[19]
GPIO_1_D20 PIN_A14 GPIO Connection 1[20]
GPIO_1_D21 PIN_B15 GPIO Connection 1[21]
GPIO_1_D22 PIN_C15 GPIO Connection 1[22]
GPIO_1_D23 PIN_E14 GPIO Connection 1[23]
GPIO_1_D24 PIN_E15 GPIO Connection 1[24]
GPIO_1_D25 PIN_E16 GPIO Connection 1[25]
GPIO_1_D26 PIN_F14 GPIO Connection 1[26]
GPIO_1_D27 PIN_F15 GPIO Connection 1[27]
GPIO_1_D28 PIN_F13 GPIO Connection 1[28]
GPIO_1_D29 PIN_F12 GPIO Connection 1[29]
GPIO_1_D30 PIN_G16 GPIO Connection 1[30]
GPIO_1_D31 PIN_G15 GPIO Connection 1[31]
GPIO_1_D32 PIN_G13 GPIO Connection 1[32]
GPIO_1_D33 PIN_G12 GPIO Connection 1[33]
GPIO_1_D34 PIN_J17 GPIO Connection 1[34]
GPIO_1_D35 PIN_K16 GPIO Connection 1[35]
3
3
.
.
6
6
U
U
s
s
i
i
n
n
g
g
V
V
G
G
A
A
The DE0-CV board includes a 16-pin D-SUB connector for VGA output. The VGA synchronization
signals are provided directly from the Cyclone V FPGA, and a 4-bit DAC using resistor network is
used to produce the analog data signals (red, green, and blue).
The associated schematic is given in
Figure 3-13 and can support standard VGA resolution (640x480 pixels, at 25 MHz).
Figure 3-13 Connections between the FPGA and VGA