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DE0-CV User Manual

38

www.terasic.com

May 4, 2015

The top-level design file contains a top-level Verilog HDL wrapper for users to add their own
design/logic. The Quartus II setting file contains information such as FPGA device type, top-level
pin assignment, and the I/O standard for each user-defined I/O pin.

Finally, the Quartus II programmer is used to download .sof file to the development board via JTAG
interface.

Figure 4-1 Design flow of building a project from the beginning to the end

4. 3

Using DE0-CV System Builder

This section provides the procedures in details on how to use the DE0-CV System Builder.



Install and Launch the DE0-CV System Builder

The DE0-CV System Builder is located in the directory:

“

Tools\SystemBuilder

”

of the DE0-CV

System CD. Users can copy the entire folder to a host computer without installing the utility. A
window will pop up, as shown in

Figure 4-2

, after executing the DE0-CV SystemBuilder.exe on the

host computer.

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Summary of Contents for DE0-CV

Page 1: ...DE0 CV User Manual 1 www terasic com May 4 2015 ...

Page 2: ...ttons 12 2 4 SDRAM Controller and Programmer 12 2 5 SD Card 14 2 6 VGA 15 2 7 Overall Structure of the DE0 CV Control Panel 16 Chapter 3 Using the Starter Kit 18 3 1 Configuration of Cyclone V FPGA on DE0 CV 18 3 2 Using the LEDs and Switches 21 3 3 Using the 7 segment Displays 25 3 4 Clock Circuitry 27 3 5 Using 2x20 GPIO Expansion Headers 27 3 6 Using VGA 30 3 7 PS 2 Serial Port 32 3 8 Micro SD ...

Page 3: ...y 4 2015 Chapter 5 Examples of Advanced Demonstrations 43 5 1 DE0 CV Factory Configuration 43 5 2 SDRAM Test in Nios II 45 5 3 SDRAM Test in Verilog 48 5 4 PS 2 Mouse Demonstration 49 5 5 Micro SD Card file system read 53 5 6 VGA Pattern 57 ...

Page 4: ... capture cards and handheld devices The DE0 CV development board includes hardware such as on board USB Blaster video capabilities and much more By leveraging all of these capabilities the DE0 CV is the perfect solution for showcasing evaluating and prototyping the true potential of the Altera Cyclone V FPGA The DE0 CV contains all components needed to use the board in conjunction with a computer ...

Page 5: ...gns and device datasheets User can download this System CD from the web http cd de0 cv terasic com 1 1 3 3 L La ay yo ou ut t a an nd d C Co om mp po on ne en nt ts s This section presents the features and design characteristics of the board A photograph of the board is shown in Figure 1 2 and Figure 1 3 It depicts the layout of the board and indicates the location of the connectors and key compon...

Page 6: ...jects The following hardware is provided on the board F FP PG GA A D De ev vi ic ce e Cyclone V 5CEBA4F23C7N Device 49K Programmable Logic Elements 3080 Kbits embedded memory 4 Fractional PLLs C Co on nf fi ig gu ur ra at ti io on n a an nd d D De eb bu ug g Serial Configuration device EPCS64 on FPGA On Board USB Blaster Normal type B USB connector JTAG and AS mode configuration supported M Me em ...

Page 7: ...mode for Micro SD Card access S Sw wi it tc ch he es s B Bu ut tt to on ns s a an nd d L LE ED Ds s 10 LEDs 10 Slide Switches 4 Debounced Push Buttons 1 CPU reset Push Buttons Six 7 Segments P Po ow we er r 5V DC input 1 1 4 4 B Bl lo oc ck k D Di ia ag gr ra am m o of f t th he e C Cy yc cl lo on ne e V V S St ta ar rt te er r B Bo oa ar rd d Figure 1 4 gives the block diagram of the board To pro...

Page 8: ...ram 1 1 5 5 G Ge et tt ti in ng g H He el lp p Here are the addresses where you can get help if you encounter any problem Terasic Inc 9F No 176 Sec 2 Gongdao 5th Rd East Dist Hsinchu City 30070 Taiwan Email support terasic com Tel 886 3 5750 880 Web http www DE0 CV terasic com ...

Page 9: ...der to your host computer and launch the control panel by executing the DE0CV_ControlPanel exe Specific control circuits should be downloaded to your FPGA board before the control panel can request it to perform required tasks The program will call Quartus II tools to download the control circuit to the FPGA board through the USB Blaster USB 0 connection To activate the Control Panel perform the f...

Page 10: ...ome LEDs and observing the result on the DE0 CV board Figure 2 1 The DE0 CV Control Panel The concept of the DE0 CV Control Panel is illustrated in Figure 2 2 The Control Circuit that performs the control functions is implemented in the FPGA board It communicates with the Control Panel window which is active on the host computer via the USB Blaster link The graphical interface is used to send comm...

Page 11: ...f reading writing a word or an entire file from to the Memory allows the user to develop multimedia applications without worrying about how to build a Memory Programmer 2 2 2 2 C Co on nt tr ro ol ll li in ng g t th he e L LE ED Ds s 7 7 s se eg gm me en nt t D Di is sp pl la ay ys s A simple function of the Control Panel is to allow setting the values displayed on LEDs 7 segment displays Choosing...

Page 12: ...he 7 SEG tab leads to the window shown in Figure 2 4 From the window directly use the left right arrows to control the 7 SEG patterns on the DE0 CV board which are updated immediately Note that the dots of the 7 SEGs are not enabled on the DE0 CV board Figure 2 4 Controlling 7 SEG display ...

Page 13: ...time and show the status in a graphical user interface It can be used to verify the functionality of the slide switches and push buttons Figure 2 5 Monitoring switches and buttons The ability to check the status of push button and slide switch is not needed in typical design activities However it provides users a simple mechanism to verify if the buttons and switches are functioning correctly Thus...

Page 14: ...RAM as follows 1 Specify the starting address in the Address box 2 Specify the number of bytes to be written in the Length box If the entire file is to be loaded then a checkmark may be placed in the File Length box instead of giving the number of bytes 3 To initiate the writing process click on the Write a File to Memory button 4 When the Control Panel responds with the standard Windows dialog bo...

Page 15: ...Content to a File button 4 When the Control Panel responds with the standard Windows dialog box asking for the destination file specify the desired file in the usual manner 2 2 5 5 S SD D C Ca ar rd d The function is designed to read the identification and specification information of the SD Card The 4 bit SD MODE is used to access the SD Card This function can be used to verify the functionality ...

Page 16: ...rn to LCD CRT monitor using the DE0 CV board Follow the steps below to generate the VGA pattern function Choosing the VGA tab leads to the window in Figure 2 8 Plug a D sub cable to the VGA connector of the DE0 CV board and LCD CRT monitor The LCD CRT monitor will display the same color pattern on the control panel window Click the drop down menu shown in Figure 2 8 where you can output the select...

Page 17: ...y The software part is implemented in C code the hardware part is implemented in Verilog HDL code with Qsys builder The source code is not available on the DE0 CV System CD To run the Control Panel users should follow the configuration setting according to Section 3 1 Figure 2 9 depicts the structure of the Control Panel Each input output device is controlled by the Nios II Processor instantiated ...

Page 18: ...DE0 CV User Manual 17 www terasic com May 4 2015 Figure 2 9 The block diagram of the DE0 CV control panel ...

Page 19: ...ming named after the IEEE standards Joint Test Action Group the configuration bit stream is downloaded directly into the Cyclone V FPGA The FPGA will retain this configuration as long as power is applied to the board the configuration information will be lost when the power is turned off 2 AS programming In this method called Active Serial programming the configuration bit stream is downloaded int...

Page 20: ...is applied to the DE0 CV board Configure the JTAG programming circuit by setting the RUN PROG slide switch SW10 to the RUN position See Figure 3 2 Connect the USB cable provided to the USB Blaster port on the DE0 CV board The FPGA can now be programmed by using the Quartus II Programmer to select a configuration bit stream file with the sof filename extension Figure 3 1 The JTAG configuration sche...

Page 21: ... DE0 CV board Configure the JTAG programming circuit by setting the RUN PROG slide switch SW10 to the PROG position The EPCS64 chip can now be programmed by using the Quartus II Programmer to select a configuration bit stream file with the pof filename extension Once the programming operation is finished set the RUN PROG slide switch back to the RUN position and then reset the board by turning the...

Page 22: ... 3 V Power Illuminates when 3 3 V power is active D16 ULED Illuminates when the on board USB Blaster is working Figure 3 4 Status LED position 3 3 2 2 U Us si in ng g t th he e L LE ED Ds s a an nd d S Sw wi it tc ch he es s User Defined Push buttons The board includes four user defined push buttons and one FPGA reset button that allow users to interact with the Cyclone V device as shown in Figure...

Page 23: ...tween the push button and Cyclone V FPGA Pushbutton released Pushbutton depressed Before Debouncing Schmitt Trigger Debounced Figure 3 6 Switch debouncing User Defined Slide Switch There are ten slide switches connected to FPGA on the board See Figure 3 7 These switches are not debounced and are assumed for use as level sensitive data inputs to a circuit Each switch is connected directly to a pin ...

Page 24: ...ollable LEDs connected to FPGA on the board Each LED is driven directly by a pin on the Cyclone V FPGA driving its associated pin to a high logic level turns the LED on and driving the pin low turns it off Figure 3 8 shows the connections between LEDs and Cyclone V FPGA Table 3 2 Table 3 3 and Table 3 4 list the pin assignment of user push buttons switches and LEDs ...

Page 25: ...utton 2 KEY3 PIN_M6 Push button 3 RESET_N PIN_P22 Push button which connected to DEV_CLRN Pin of FPGA Table 3 3 Pin Assignment of Slide Switches Signal Name FPGA Pin No Description SW0 PIN_U13 Slide Switch 0 SW1 PIN_V13 Slide Switch 1 SW2 PIN_T13 Slide Switch 2 SW3 PIN_T12 Slide Switch 3 SW4 PIN_AA15 Slide Switch 4 SW5 PIN_AB15 Slide Switch 5 SW6 PIN_AA14 Slide Switch 6 SW7 PIN_AA13 Slide Switch 7...

Page 26: ...are paired to display numbers in various sizes Figure 3 9 shows the connection of seven segments common anode to pins on Cyclone V FPGA The segment can be turned on or off by applying a low logic level or high logic level from the FPGA respectively Each segment in a display is indexed from 0 to 6 with corresponding positions given in Figure 3 9 Table 3 5 shows the pin assignment of FPGA to the 7 s...

Page 27: ...Segment Digit 2 4 HEX25 PIN_AB22 Seven Segment Digit 2 5 HEX26 PIN_AB21 Seven Segment Digit 2 6 HEX30 PIN_Y16 Seven Segment Digit 3 0 HEX31 PIN_W16 Seven Segment Digit 3 1 HEX32 PIN_Y17 Seven Segment Digit 3 2 HEX33 PIN_V16 Seven Segment Digit 3 3 HEX34 PIN_U17 Seven Segment Digit 3 4 HEX35 PIN_V18 Seven Segment Digit 3 5 HEX36 PIN_V19 Seven Segment Digit 3 6 HEX40 PIN_U20 Seven Segment Digit 4 0 ...

Page 28: ...K3_50 PIN_E10 50 MHz clock input Bank 8A CLOCK4_50 PIN_V15 50 MHz clock input Bank 4A 3 3 5 5 U Us si in ng g 2 2x x2 20 0 G GP PI IO O E Ex xp pa an ns si io on n H He ea ad de er rs s The board has two 40 pin expansion headers Each header has 36 user pins connected directly to the Cyclone V FPGA It also comes with DC 5V VCC5 DC 3 3V VCC3P3 and two GND pins Both 5V and 3 3V can provide a total of...

Page 29: ...ion headers Table 3 7 Pin Assignment of Expansion Headers Signal Name FPGA Pin No Description GPIO_0_D0 PIN_N16 GPIO Connection 0 0 GPIO_0_D1 PIN_B16 GPIO Connection 0 1 GPIO_0_D2 PIN_M16 GPIO Connection 0 2 GPIO_0_D3 PIN_C16 GPIO Connection 0 3 GPIO_0_D4 PIN_D17 GPIO Connection 0 4 GPIO_0_D5 PIN_K20 GPIO Connection 0 5 GPIO_0_D6 PIN_K21 GPIO Connection 0 6 ...

Page 30: ...D27 PIN_P18 GPIO Connection 0 27 GPIO_0_D28 PIN_R15 GPIO Connection 0 28 GPIO_0_D29 PIN_R17 GPIO Connection 0 29 GPIO_0_D30 PIN_R16 GPIO Connection 0 30 GPIO_0_D31 PIN_T20 GPIO Connection 0 31 GPIO_0_D32 PIN_T19 GPIO Connection 0 32 GPIO_0_D33 PIN_T18 GPIO Connection 0 33 GPIO_0_D34 PIN_T17 GPIO Connection 0 34 GPIO_0_D35 PIN_T15 GPIO Connection 0 35 GPIO_1_D0 PIN_H16 GPIO Connection 1 0 GPIO_1_D1...

Page 31: ...12 GPIO Connection 1 29 GPIO_1_D30 PIN_G16 GPIO Connection 1 30 GPIO_1_D31 PIN_G15 GPIO Connection 1 31 GPIO_1_D32 PIN_G13 GPIO Connection 1 32 GPIO_1_D33 PIN_G12 GPIO Connection 1 33 GPIO_1_D34 PIN_J17 GPIO Connection 1 34 GPIO_1_D35 PIN_K16 GPIO Connection 1 35 3 3 6 6 U Us si in ng g V VG GA A The DE0 CV board includes a 16 pin D SUB connector for VGA output The VGA synchronization signals are ...

Page 32: ...GB signals must again be off before the next hsync pulse can occur The timing of vertical synchronization vsync is similar to the one shown in Figure 3 14 except that a vsync pulse signifies the end of one frame and the start of the next and the data refers to the set of rows in the frame horizontal timing Table 3 8 and Table 3 9 show different resolutions and durations of time period a b c and d ...

Page 33: ... 3 3 7 7 P PS S 2 2 S Se er ri ia al l P Po or rt t The DE0 CV board comes with a standard PS 2 interface and a connector for a PS 2 keyboard or mouse Figure 3 15 shows the connection of PS 2 circuit to the FPGA Users can use the PS 2 keyboard and mouse on the DE0 CV board simultaneously by a PS 2 Y Cable as shown in Figure 3 16 Instructions on how to use PS 2 mouse and or keyboard can be found on...

Page 34: ... second PS 2 device PS2_DAT2 PIN_G1 PS 2 Data reserved for second PS 2 device 3 3 8 8 M Mi ic cr ro o S SD D C Ca ar rd d S So oc ck ke et t The development board supports Micro SD card interface using x4 data lines Figure 3 17 shows the related signals connections between the SD Card and Cyclone V FPGA and Figure 3 18 shows micro SD card plug in position Finally Table 3 12 lists all the associate...

Page 35: ...SD_DATA1 PIN_D12 Serial Data 1 SD_DATA2 PIN_E12 Serial Data 2 SD_DATA3 PIN_C11 Serial Data 3 3 3 9 9 U Us si in ng g S SD DR RA AM M The board features 64MB of SDRAM with a single 64MB 32Mx16 SDRAM chip The chip consists of 16 bit data line control line and address line connected to the FPGA This chip uses the 3 3V LVCMOS signaling standard Connections between the FPGA and SDRAM are shown in Figur...

Page 36: ...10 SDRAM Address 5 DRAM_ADDR6 PIN_P12 SDRAM Address 6 DRAM_ADDR7 PIN_P7 SDRAM Address 7 DRAM_ADDR8 PIN_P8 SDRAM Address 8 DRAM_ADDR9 PIN_R5 SDRAM Address 9 DRAM_ADDR10 PIN_U8 SDRAM Address 10 DRAM_ADDR11 PIN_P6 SDRAM Address 11 DRAM_ADDR12 PIN_R7 SDRAM Address 12 DRAM_DQ0 PIN_Y9 SDRAM Data 0 DRAM_DQ1 PIN_T10 SDRAM Data 1 DRAM_DQ2 PIN_R9 SDRAM Data 2 DRAM_DQ3 PIN_Y11 SDRAM Data 3 DRAM_DQ4 PIN_R10 S...

Page 37: ...AM_DQ15 PIN_T9 SDRAM Data 15 DRAM_BA0 PIN_T7 SDRAM Bank Address 0 DRAM_BA1 PIN_AB7 SDRAM Bank Address 1 DRAM_LDQM PIN_U12 SDRAM byte Data Mask 0 DRAM_UDQM PIN_N8 SDRAM byte Data Mask 1 DRAM_RAS_N PIN_AB6 SDRAM Row Address Strobe DRAM_CAS_N PIN_V6 SDRAM Column Address Strobe DRAM_CKE PIN_R6 SDRAM Clock Enable DRAM_CLK PIN_AB11 SDRAM Clock DRAM_WE_N PIN_AB5 SDRAM Write Enable DRAM_CS_N PIN_U6 SDRAM ...

Page 38: ...s that are prone to compilation error when users manually edit the top level design file or place pin assignment The common mistakes that users encounter are Board is damaged due to incorrect bank voltage setting or pin assignment Board is malfunctioned because of wrong device chosen declaration of pin location or direction is incorrect or forgotten Performance degradation due to improper pin assi...

Page 39: ... the development board via JTAG interface Figure 4 1 Design flow of building a project from the beginning to the end 4 3 Using DE0 CV System Builder This section provides the procedures in details on how to use the DE0 CV System Builder Install and Launch the DE0 CV System Builder The DE0 CV System Builder is located in the directory Tools SystemBuilder of the DE0 CV System CD Users can copy the e...

Page 40: ... 4 2 The GUI of DE0 CV System Builder Enter Project Name Enter the project name in the circled area as shown in Figure 4 3 The project name typed in will be assigned automatically as the name of your top level design entity Figure 4 3 Enter the project name ...

Page 41: ...the DE0 CV System Builder will automatically generate its associated pin assignment including the pin name pin location pin direction and I O standard Figure 4 4 System configuration group GPIO Expansion If users connect any Terasic GPIO based daughter card to the GPIO connector s on DE0 CV the DE0 CV System Builder can generate a project that include the corresponding module as shown in Figure 4 ...

Page 42: ... feature that denote the pin name of the daughter card assigned in your design Users may leave this field blank Project Setting Management The DE0 CV System Builder also provides the option to load a setting or save users current board configuration in cfg file as shown in Figure 4 6 Figure 4 6 Project Settings ...

Page 43: ...rtus Project Table 4 1 Files generated by the DE0 CV System Builder No Filename Description 1 Project name v Top level Verilog HDL file for Quartus II 2 Project name qpf Quartus II Project File 3 Project name qsf Quartus II Setting File 4 Project name sdc Synopsis Design Constraints file for Quartus II 5 Project name htm Pin Assignment Document Users can add custom logic into the project in Quartu...

Page 44: ... your local directory contains NO space Otherwise it will lead to error in Nios II Note Quartus II v14 0 or later is required for all DE0 CV demonstrations to support Cyclone V FPGA device 5 5 1 1 D DE E0 0 C CV V F Fa ac ct to or ry y C Co on nf fi ig gu ur ra at ti io on n The DE0 CV board has a default configuration bit stream pre programmed which demonstrates some of the basic features onboard...

Page 45: ...tch file pof_DE0_CV_Default bat for USB Blaster under the batch file folder DE0_CV_Default demo_batch 5 Once the programming operation is finished set the RUN PROG slide switch back to the RUN position and then reset the board by turning the power switch off and back on this action causes the new configuration data in the EPCS64 device to be loaded into the FPGA chip Configuring the EPCS64 with JI...

Page 46: ...DRAM controller IP accesses SDRAM and how the Nios II processor reads and writes the SDRAM for hardware verification The SDRAM controller handles complex aspects of accessing SDRAM such as initializing the memory device managing SDRAM banks and keeping the devices refreshed at certain interval System Block Diagram Figure 5 2 shows the system block diagram of this demonstration The system requires ...

Page 47: ...program will show the progress in nios terminal when writing reading data to from the SDRAM When the verification process reaches 100 the result will be displayed in nios terminal D De es si ig gn n T To oo ol ls s Quartus II v14 0 Nios II Eclipse v14 0 D De em mo on ns st tr ra at ti io on n S So ou ur rc ce e C Co od de e Quartus project directory DE0_CV_SDRAM_Nios_Test Nios II Eclipse directory...

Page 48: ...s II v14 0 and Nios II v14 0 must be pre installed on the host PC Power on the DE0_CV board Connect the DE0_CV board J13 to the host PC with a USB cable and install the USB Blaster driver if necessary Execute the demo batch file DE0_CV_SDRAM_Nios_Test bat from the directory DE0_CV_SDRAM_Nios_Test demo_batch After the program is downloaded and executed successfully a prompt message will be displaye...

Page 49: ...nd generates 100 MHz as the memory clock Figure 5 4 Block diagram of the SDRAM test in Verilog RW_Test module writes the entire memory with a test sequence first before comparing the data read back with the regenerated test sequence which is same as the data written to the memory KEY0 triggers test control signals for the SDRAM and the LEDs will indicate the test result according to Table 5 1 D De...

Page 50: ...0 is then released LEDR1 and LEDR2 should start blinking After approximately 8 seconds LEDR1 should stop blinking and stay ON to indicate the test is PASS Table 5 1 lists the status of LED indicators If LEDR2 is not blinking it means 50MHz clock source is not working If LEDR1 failed to remain ON after approximately 8 seconds the SDRAM test is NG Press KEY0 again to repeat the SDRAM test Table 5 1 ...

Page 51: ... it first pulls the clock line low for more than one clock cycle to inhibit the current transmission process or to indicate the start of a new transmission process which is usually called as inhibit state It then pulls low the data line before releasing the clock line This is called the request state The rising edge on the clock line formed by the release action can also be used to indicate the sa...

Page 52: ...t ti io on n S So ou ur rc ce e C Co od de e Project directory DE0_CV_PS2_DEMO Bitstream used DE0_CV_PS2_DEMO sof D De em mo on ns st tr ra at ti io on n B Ba at tc ch h F Fi il le e Demo batch file directoy DE0_CV_PS2_DEMO demo_batch The folder includes the following files Batch file DE0_CV_PS2_DEMO bat FPGA configuration file DE0_CV_PS2_DEMO sof ...

Page 53: ...e FPGA by executing DE0_CV_PS2_DEMO demo_batch DE0_CV_PS2_DEMO bat Plug in the PS 2 mouse Press KEY0 to enable data transfer Press KEY1 to clear the display data cache The 7 segment display should change when the PS 2 mouse moves The LEDR 2 0 will blink according to Figure 5 6 and Table 5 2 when the left button right button and or middle button is pressed Figure 5 6 Description of 7 segment Displa...

Page 54: ... for Micro SD Card access In this demonstration we will show how to browse files stored in the root directory of an SD Card and how to read the file contents of a specific file The Micro SD Card is required to be formatted as FAT File System in advance Long file name is supported in this demonstration Figure 5 7 shows the hardware system block diagram of this demonstration The system requires a 50...

Page 55: ...D Card is inserted If an MicroSD Card is found it will check whether the MicroSD Card is formatted as FAT file system If so it searches all files in the root directory of the FAT file system and displays their names in the Nios II terminal If a text file named test txt is found it will dump the file contents If it successfully recognizes the FAT file system it will turn on the LEDR4 LEDR0 On the o...

Page 56: ...V_SD_DEMO sof Nios II Program DE0_CV_SD_DEMO elf D De em mo on ns st tr ra at ti io on n S Se et tu up p Make sure Quartus II and Nios II are installed on your PC Power on the DE0 CV board Connect USB Blaster to the DE0 CV board and install USB Blaster driver if necessary Execute the demo batch file DE0_CV_SD_DEMO bat for USB Blaster II under the batch file folder DE0_CV_SD_DEMO demo_batch After N...

Page 57: ...ay 4 2015 Figure 5 9 Insert the Micro SD card into DE0 CV Press KEY3 of the DE0 CV board to start reading SD Card The program will display SD Card information as shown in Figure 5 10 Figure 5 10 Running result of SD_CARD demo on DE0 CV board ...

Page 58: ...d data output Please refer to the chapter 3 6 in DE0_CV_User_Manual on the DE0_CVSystem CD for detailed information of using the VGA output As shown in Figure 5 12 the RGB data drives each pixel in turn across the row being displayed after the time period of back porch Figure 5 11 Block diagram of the VGA Pattern demonstration Figure 5 12 Timing Waveform of VGA interface D De es si ig gn n T To oo...

Page 59: ...installed to the host PC Power on the DE0 CV board Connect USB Blaster to the DE0 CV board and install USB Blaster driver if necessary Connect VGA D SUB to a VGA monitor Execute the demo batch file DE0_CV_VGA_Pattern bat from the directory DE0_CV_VGA_Pattern demo_batch The VGA monitor will display a color pattern Figure 5 13 illustrates the setup for this demonstration Figure 5 13 The setup for th...

Page 60: ...p if you encounter problems Terasic Inc 9F No 176 Sec 2 Gongdao 5th Rd East Dist Hsinchu City 30070 Taiwan Email support terasic com Web www terasic com DE0 CV Web www DE0 CV terasic com R Re ev vi is si io on n H Hi is st to or ry y Date Version Changes 2014 12 First publication 2015 04 Document revision 2015 5 Modified DE0 CV package content figure ...

Page 61: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Terasic P0192 ...

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