DE0-CV User Manual
27
www.terasic.com
May 4, 2015
3
3
.
.
4
4
C
C
l
l
o
o
c
c
k
k
C
C
i
i
r
r
c
c
u
u
i
i
t
t
r
r
y
y
Figure 3-10
shows the clock circuit of DE0-CV Board, the crystal 50 MHz buffered to four 50MHz
clock. The associated pin assignment for clock inputs to FPGA I/O pins is listed in
Table 3-6.
Figure 3-10 Clock circuit of the FPGA Board
Table 3-6 Pin Assignment of Clock Inputs
Signal Name
FPGA Pin No.
Description
CLOCK_50
PIN_M9
50 MHz clock input(Bank 3B)
CLOCK2_50
PIN_H13
50 MHz clock input(Bank 7A)
CLOCK3_50
PIN_E10
50 MHz clock input(Bank 8A)
CLOCK4_50
PIN_V15
50 MHz clock input(Bank 4A)
3
3
.
.
5
5
U
U
s
s
i
i
n
n
g
g
2
2
x
x
2
2
0
0
G
G
P
P
I
I
O
O
E
E
x
x
p
p
a
a
n
n
s
s
i
i
o
o
n
n
H
H
e
e
a
a
d
d
e
e
r
r
s
s
The board has two 40-pin expansion headers. Each header has 36 user pins connected directly to the
Cyclone V FPGA. It also comes with DC +5V (VCC5), DC +3.3V (VCC3P3), and two GND pins.
Both 5V and 3.3V can provide a total of 5W power.
Each pin on the expansion headers is connected to two diodes and a resistor for protection against
high or low voltage level.
Figure 3-11
shows the protection circuitry applied to all 2x36 data pins.
Figure 3-11
shows the related schematics.
Table 3-7
shows the pin assignment of two GPIO
headers.
