DE0-CV User Manual
31
www.terasic.com
May 4, 2015
The timing specification for VGA synchronization and RGB (red, green, blue) data can be easily
found on website nowadays.
Figure 3-13
illustrates the basic timing requirements for each row
(horizontal) displayed on a VGA monitor. An active-low pulse of specific duration is applied to the
horizontal synchronization (hsync) input of the monitor, which signifies the end of one row of data
and the start of the next. The data (RGB) output to the monitor must be off (driven to 0 V) for a
time period called the back porch (b) after the hsync pulse occurs, which is followed by the display
interval (c). During the data display interval the RGB data drives each pixel in turn across the row
being displayed. Finally, there is a time period called the front porch (d) where the RGB signals
must again be off before the next hsync pulse can occur. The timing of vertical synchronization
(vsync) is similar to the one shown in
Figure 3-14
, except that a vsync pulse signifies the end of
one frame and the start of the next, and the data refers to the set of rows in the frame (horizontal
timing).
Table 3-8
and
Table 3-9
show different resolutions and durations of time period a, b, c, and
d for both horizontal and vertical timing.
The pin assignments between the Cyclone V FPGA and the VGA connector are listed
in
Table
3-10
.
Figure 3-14 VGA horizontal timing specification
Table 3-8 VGA Horizontal Timing Specification
VGA mode
Horizontal Timing Spec
Configuration
Resolution(HxV)
a(pixel
clock
cycle)
b(pixel
clock
cycle)
c(pixel
clock
cycle)
d(pixel
clock
cycle)
Pixel clock(MHz)
VGA(60Hz)
640x480
96
48
640
16
25
Table 3-9 VGA Vertical Timing Specification
VGA mode
Vertical Timing Spec
Configuration
Resolution(HxV)
a(lines) b(lines) c(lines) d(lines) Pixel clock(MHz)
VGA(60Hz)
640x480
2
33
480
10
25
