DE0-CV User Manual
16
www.terasic.com
May 4, 2015
Figure 2-8 Controlling VGA display under Control Panel
2
2
.
.
7
7
O
O
v
v
e
e
r
r
a
a
l
l
l
l
S
S
t
t
r
r
u
u
c
c
t
t
u
u
r
r
e
e
o
o
f
f
t
t
h
h
e
e
D
D
E
E
0
0
-
-
C
C
V
V
C
C
o
o
n
n
t
t
r
r
o
o
l
l
P
P
a
a
n
n
e
e
l
l
The DE0-CV Control Panel is based on a Nios II Qsys system instantiated in the Cyclone V FPGA
with software running on the on-chip memory. The software part is implemented in C code; the
hardware part is implemented in Verilog HDL code with Qsys builder. The source code is not
available on the DE0-CV System CD.
To run the Control Panel, users should follow the configuration setting according to Section 3.1.
Figure 2-9
depicts the structure of the Control Panel. Each input/output device is controlled by the
Nios II Processor instantiated in the FPGA chip. The communication with the PC is done via the
USB Blaster link. The Nios II interprets the commands sent from the PC and performs the
corresponding actions.
