DE0-CV User Manual
48
www.terasic.com
May 4, 2015
5
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.
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V
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DE0_CV system CD offers another SDRAM test with its test code written in Verilog HDL. The
memory size of the SDRAM bank tested is still 64MB.
Function Block Diagram
Figure 5-4
shows the function block diagram of this demonstration. The SDRAM controller uses 50
MHz as a reference clock and generates 100 MHz as the memory clock.
Figure 5-4 Block diagram of the SDRAM test in Verilog
RW_Test module writes the entire memory with a test sequence first before comparing the data read
back with the regenerated test sequence, which is same as the data written to the memory. KEY0
triggers test control signals for the SDRAM, and the LEDs will indicate the test result according to
Table 5-1
.
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n
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T
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Quartus II v14.0
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Project directory: DE0_CV_SDRAM_RTL_Test
Bitstream used: DE0_CV_SDRAM_RTL_Test.sof
