DE0-CV User Manual
49
www.terasic.com
May 4, 2015
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Demo batch file folder: \DE0_CV_SDRAM_RTL_Test\demo_batch
The directory includes the following files:
Batch file: DE0_CV_SDRAM_RTL_Test.bat
FPGA configuration file: DE0_CV_SDRAM_RTL_Test.sof
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Quartus II v14.0 must be pre-installed to the host PC.
Connect the DE0_CV board (J13) to the host PC with a USB cable and install the USB-Blaster II
driver if necessary
Power on the DE0_CV board.
Execute the demo batch file “ DE0_CV_SDRAM_RTL_Test.bat” from the directoy
\DE0_CV_SDRAM_RTL_Test \demo_batch.
Press
KEY0
on the DE0_CV board to start the verification process. When
KEY0
is pressed, the
LEDR
[2:0] should turn on. When
KEY0
is then released,
LEDR1
and
LEDR2
should start
blinking.
After approximately 8 seconds,
LEDR1
should stop blinking and stay ON to indicate the test is
PASS.
Table 5-1
lists the status of
LED
indicators.
If
LEDR2
is not blinking, it means 50MHz clock source is not working.
If
LEDR1
failed to remain ON after approximately 8 seconds, the SDRAM test is NG.
Press
KEY0
again to repeat the SDRAM test.
Table 5-1 Status of LED Indicators
Name
Description
LEDR1
ON if the test is PASS after releasing KEY0
LEDR2
Blinks
5
5
.
.
4
4
P
P
S
S
/
/
2
2
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A simply PS/2 controller coded in Verilog HDL is provided to demonstrate bi-directional
communication with a PS/2 mouse. A comprehensive PS/2 controller can be developed based on it
and more sophisticated functions can be implemented such as setting the sampling rate or resolution,
which needs to transfer two data bytes at once.
More information about the PS/2 protocol can be found on various websites.
