Teledyne SP Devices ADQ7DC, Manual

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19-2233 PC2
2019-02-01
2(50)
ADQ7DC Manual
16-1796 PC2 2019-02-01
2(50)
Table of content
1 INTRODUCTION ........................................................................................................... 5
1.1 ADQ7DC Architecture.................................................................................................... 5
1.2 Fundamental design properties ..................................................................................... 5
1.2.1 Data format .................................................................................................................................. 6
1.2.2 Calibration.................................................................................................................................... 6
1.2.3 Data acquisition nomenclature .................................................................................................... 6
1.2.4 ADQ7DC sampling clock frequency ............................................................................................ 7
1.2.5 System clocks.............................................................................................................................. 7
1.2.6 Analog signal range ..................................................................................................................... 7
2 SETTING UP THE ANALOG FRONT-END ................................................................... 9
2.1 AFE block diagram......................................................................................................... 9
2.2 Set analog DC-offset...................................................................................................... 9
2.3 Adjusting the digital gain and offset ............................................................................. 10
3 SIGNAL QUALITY ENHANCEMENT........................................................................... 11
3.1 Digital Baseline Stabilizer ............................................................................................ 11
3.2 Interleaving correction ADX ......................................................................................... 11
4 TRIGGER..................................................................................................................... 12
4.1 Trigger block diagram .................................................................................................. 12
4.2 Position of the trigger in the data ................................................................................. 13
4.3 Timestamp ................................................................................................................... 13
4.3.1 Timestamp definitions................................................................................................................ 13
4.3.2 Timestamp reset ........................................................................................................................ 14
4.4 Blocking triggers for synchronization ........................................................................... 16
4.4.1 Function overview...................................................................................................................... 16
4.4.2 Block triggers once .................................................................................................................... 17
4.4.3 Windowing triggers .................................................................................................................... 17
4.4.4 Gating and windowing triggers .................................................................................................. 17
4.4.5 Programming sequence for using trigger blocking .................................................................... 17
4.5 Trigger jitter.................................................................................................................. 18
4.5.1 Trigger jitter definitions .............................................................................................................. 18
4.5.2 Asynchronous triggering ............................................................................................................ 18
4.5.3 Synchronous trigger................................................................................................................... 19
4.5.4 Extended trigger resolution........................................................................................................ 19
4.6 Software trigger............................................................................................................ 19
4.7 External Trigger Inputs................................................................................................. 20
4.7.1 External trigger TRIG front panel connector .............................................................................. 20
4.7.2 External trigger SYNC connector............................................................................................... 21
4.7.3 Driving the external TRIG/SYNC signal by controlling input impedance ................................... 21
4.8 External trigger in the backplane ................................................................................. 22
4.8.1 PXIe interface ............................................................................................................................ 22
4.8.2 MTCA.4 interface....................................................................................................................... 23
4.9 Level trigger ................................................................................................................. 24
4.9.1 Setting the level trigger level...................................................................................................... 25
4.9.2 Level trigger and DBS................................................................................................................ 25
4.9.3 Controlling noise sensitivity ....................................................................................................... 25
4.10 Internal trigger.............................................................................................................. 26
4.11 Trigger output............................................................................................................... 26
4.11.1Trigger output port selection ...................................................................................................... 26
4.11.2Frame sync output on SYNC connector .................................................................................... 27