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ADQ7DC Manual
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The connector on the front panel accepts a clock reference from external equipment. The clock refer-
ence quality is improved in a jitter cleaning circuitry. To match the tuning of the jitter cleaning circuitry
the clock reference has to be 10 MHz.
The PXI Express and MTCA.4 allows clock reference input from the backplane, and can then benefit
from the infrastructure of the chassis.
5.6 Internal clock generator
There is an internal high quality clock generator that is used for generating the Sampling Clock for the
A/D converters. The data and trigger clocks are also generated by this clock generator.
5.7 External clock
If the system is designed with an external high quality signal it may be used for clocking the ADQ. The
external clock frequency must be 2.5 GHz for both 5 GSPS and 10 GSPS modes.
If an external clock source is used, all the internal clocks are generated from that to maintain the phase
and frequency ratio.
5.8 Clock reference output
In addition to the synchronization solution with an external clock reference source, the digitizer can also
act as master and output its clock reference to external equipment. The selected clock reference
source will then be present at the clock connector on the front panel. Note that the connector is shared
with clock input.
5.9 Sample skip
The data rate out from the A/D converter is set by the sample rate of the digitizer. The data rate can be
reduced by the sample skip function. Setting the sample skip factor to, for example, 4 means that every
4th sample is kept and the others are discarded. This will efficiently reduce the data rate.
Note that there is no decimation filter in this function. Decimation filter is available in the –FW4DDC
firmware option.
