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Teledyne SP Devices ADQ7DC, Manual

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Teledyne SP Devices ADQ7DC Manual Download Page 8

19-2233 PC2 
2019-02-01

8(50)

ADQ7DC Manual

16-1796 PC2 2019-02-01

8(50)

The maximum digital code 2^15 represents an analog signal with a level 

ACTUAL_ANALOG_RANGE / 2

 

at the input. A specific analog signal 

ANALOG_LEVEL

 will then be represented by the following digital 

code: 

DIGITAL_CODE_LEVEL = ANALOG_LEVEL / ( ACTUAL_ANALOG_RANGE / 2 ) * 2^15

(1)

A specific code 

DIGITAL_CODE_LEVEL

 then represent the analog level as: 

ANALOG_LEVEL = ( DIGITAL_CODE_LEVEL / 2^15 ) * ( ACTUAL_ANALOG_RANGE / 2)

(2)

Summary of Contents for ADQ7DC

Page 1: ...com Regional sales offices www spdevices com contact Manual ADQ7DC This manual describes how to get the full potential out of Teledyne SP Devices digitizer ADQ7DC The manual includes these steps Set u...

Page 2: ...rs for synchronization 16 4 4 1 Function overview 16 4 4 2 Block triggers once 17 4 4 3 Windowing triggers 17 4 4 4 Gating and windowing triggers 17 4 4 5 Programming sequence for using trigger blocki...

Page 3: ...37 7 1 Multi thread notice 37 7 2 Acquisition memory 37 7 3 Acquisition modes 38 7 3 1 Continuous streaming acquisition 38 7 3 2 Triggered streaming acquisition 39 7 3 3 Multi record acquisition 39 7...

Page 4: ...19 2233 PC2 2019 02 01 4 50 ADQ7DC Manual 16 1796 PC2 2019 02 01 4 50...

Page 5: ...that are necessary to understand before continuing DESCRIPTION REFERENCE a Switch between 1 channel and 2 channels 2 b Signal conditioning analog front end 2 c High speed and high resolution A D conv...

Page 6: ...on During the factory calibration procedure the analog properties are measured and parameters for a digi tal compensation are computed An analog deviation in the front end is thus compensated for by t...

Page 7: ...referred to as the Data Clock See Section 5 1 for more details on the clock system 1 2 6 Analog signal range The analog signal range ACTUAL_ANALOG_RANGE is 1 Vpp and is by default symmetrical around...

Page 8: ...th a level ACTUAL_ANALOG_RANGE 2 at the input A specific analog signal ANALOG_LEVEL will then be represented by the following digital code DIGITAL_CODE_LEVEL ANALOG_LEVEL ACTUAL_ANALOG_RANGE 2 2 15 1...

Page 9: ...able The analog DC offset is applied to the signal to better adopt to the signal range of the digitizer The analog range is by default set symmetrical around zero If the sig nal is unipolar or heavily...

Page 10: ...cy of 22 bits Section 3 1 2 3 Adjusting the digital gain and offset The digital gain and offset block is primarily intended for factory calibration but it may also be accessed by the user and offers a...

Page 11: ...vergence of DBS is slowed down Note that DBS is defined for systems with a baseline and distinct short pulses DBS is not intended for sinusoidal type of signals For sinusoidal types of signals use ADX...

Page 12: ...A software trigger is available for user control SWTrig 4 6 f External trigger input from backplane in PXIe or MTCA 4 8 g External trigger input on front panel connector TRIG 4 7 1 h External trigger...

Page 13: ...rigger delay The timing of the trigger is read from the record header Section 7 6 The parameters TIME_STAMP and RECORD_START are explained in Section 4 3 1 4 3 Timestamp 4 3 1 Timestamp definitions Th...

Page 14: ...the trigger was then TRIGGER_TIME TIME_STAMP TIME_BASE 125125 ps 125 125 ns The time for the first sample in the record is RECORD_TIME TIME_STAMP RECORD_START TIME_BASE 109 000 ps 109 ns The time betw...

Page 15: ...using the external trigger and the sync is that the external trigger has the a sample resolution while the sync timing resolution is controlled by the Data Clock in the FPGA Note that the backplane tr...

Page 16: ...ources Figure 7 a b c Note the order of the commands for activating triggers and trigger blockers Figure 7 e g h i Figure 8 illustrates how the triggers are accepted or rejected in the window mode DES...

Page 17: ...er signal is a point trigger and a sync signal is a line trigger 4 4 4 Gating and windowing triggers The gate mode for blocking triggers is illustrated in Figure 7 l The length of the window where tri...

Page 18: ...The RMS value of such a process is TRIGGER_CLOCK_PERIOD sqrt 12 The highest resolution is achieved with an external trigger connected to the TRIG connector ADQ7DC has a trigger clock at 20 GSPS TRIGGE...

Page 19: ...e timestamp information Section 4 3 The position of the first sample is rounded up from the trigger position The parameter RECORD_START tells where the trigger was Referring to Figure 10 the RECORD_ST...

Page 20: ...ing or falling to adjust to the polarity of the trigger signal CONNECTOR DESCRIPTION TIME RESOLUTION TOTAL JITTER IMPEDANCE TRIG LEVEL REF TRIG External trigger on front panel 50 ps 28 ps 50 500 SW co...

Page 21: ...important for precise timing However in a high fan out situation where a trigger source has to drive many nodes the load can be too high The trigger input can then be set in a high impedance mode and...

Page 22: ...hed trigger lines from the system timing slot To use these triggers a dedicated timing generation board has to be used in the system timing slot The TRIG bus is a general bus in the back plane which c...

Page 23: ...ND REF a Backplane Trigger bus and DSTAR connections b Set direction for each port in the backplane SetDirectionPXI c Output Select output port for trigger output signal SetupTriggerOutput 4 11 d Outp...

Page 24: ...t direction for each port in the backplane SetDirectionMLVDS c Output Select output port for trigger output SetupTriggerOutput 4 11 d Output This is the source for the trigger output signal SetupTrigg...

Page 25: ...e sensitivity The level trigger is sensitive to noise since it can detect a step as small as one digital code This can cause unwanted triggering The noise sensitivity is controlled by a hysteresis fun...

Page 26: ...he first part selects the source of the trigger output signal The second part selects the physical output port for the trigger output signal Note that the trigger output is the same physical TRIG conn...

Page 27: ...cording is ongoing and will thus not generate a record Note that the timing of the trigger event in the capturing of a record is based on the Sample Clock but the trigger output is based on the Data C...

Page 28: ...reates a record from streaming data 7 Figure 19 Internal routing of internal trigger DESCRIPTION USER COMMAND REF a Internal trigger generator SetInternalTriggerPeriod 4 10 b Select internal trigger a...

Page 29: ...ger The trigger event on channel D in Figure 21 is recorded on the channel D The trigger timing is then calculated with high precision using interpola tion DESCRIPTION USER COMMAND a Select a channel...

Page 30: ...lel to maintain the throughput The Data Clock is also synchronized to the clock reference Finally the host PC interface also operate on a different clock The PCIe system clock is provided from the PCI...

Page 31: ...lock reference The free running internal clock reference of the digitizer offers high precision and is suitable for most measurements However for some applications an absolute phase lock to other part...

Page 32: ...Q The external clock frequency must be 2 5 GHz for both 5 GSPS and 10 GSPS modes If an external clock source is used all the internal clocks are generated from that to maintain the phase and frequency...

Page 33: ...nal device This is possible since the external trigger input logic always listen to the signal on the TRIG connector The following example illustrate how to trigger the digitizer and an exter nal devi...

Page 34: ...Port 1 This sends a signal on the TRIG connector that triggers the devices The GPIO input function always listen to the trigger pin This means that the external trigger pin value can always be read fr...

Page 35: ...trolled external GPIO signals b GPIO input function always reads the state of the pin The GPIO output function is activated by the user SetDirectionGPIOPort c The user may access the pin by reading an...

Page 36: ...1 GND 36 GPIO5 Single ended 3 3 V 7 GPDIC3_P LVDS input clock 22 GND 37 GPIO6 Single ended 3 3 V 8 GPDIC3_N LVDS input clock 23 GND 38 GPIO7 Single ended 3 3 V 9 GPDO4_P LVDS output 24 GND 39 GPIO8 Si...

Page 37: ...ted channels which means that if only one channel is activated the entire memory is available for that channel The data memory is also shared between data and headers Table 5 A header contains informa...

Page 38: ...re 30 This continues until stopped by the user Note that the data rate from the ADCs is up to 20 GBytes s but the data rate to the PC is limited to 6 8 GBytes s1 The continuous streaming mode thus ass...

Page 39: ...is recorded at a trigger event and has a limited distribution in time Each record has a header with timing information The effective data rate to the PC is set by the trigger rate in combination with...

Page 40: ...ance event driven data transfer This is the main mode for both continuous streaming Section 7 3 1 and triggered streaming Section 7 3 2 acquisi tion The flow is driven by the real time acquisition in...

Page 41: ...is sent in real time to the FIFO on the ADQ d The DMA is set up to transfer data to the PC e Kernel buffers in the host PC receives the data form the digitizer f The ADQAPI is set up to wait for inco...

Page 42: ...lled by the user in a schedule The user first sets up the digitizer then starts the acquisition and after that requests the data This is the straight forward method if the total amount of data is less...

Page 43: ...O on the ADQ d The DMA transfers data to the PC when requested by the user e Kernel buffers in the host PC receives the data form the digitizer f The ADQAPI receives incoming data and do necessary pre...

Page 44: ...2 The user s buffers consist of two sets of buffers one for header information and one for data The header is always 40 bytes per record and the content is described in Section 7 6 The data buffer siz...

Page 45: ...Additional information about e g the experiment is added to the header c Header and data is analyzed in real time and only requested parameters are stored 7 6 Figure 37 Data flow through the system PA...

Page 46: ...combinations are available for ADQ Development Kit users to create artificial channels 7 6 6 Record number The Record number is counting the number of records captured from the power up of the digitiz...

Page 47: ...h offset b Digital offset calibration c Digital baseline stabilizer that dynamically adjust baseline to zero That is adjust the offset Under range has already occurred prior to this stage d Acquisitio...

Page 48: ...ess electrical interface to commu nicate with the host PC Generation 1 2 and 3 up to 8 lanes is supported by the digitizer 8 3 Using several units 8 3 1 Using several digitizers from a single applicat...

Page 49: ...heet 2 14 1351 ADQAPI Reference guide 3 08 0214 ADQAPI User guide 4 18 2104 ADQ7 FWATD application note 5 17 1957 ADQ7 FWATD user guide 6 18 2059 ADQ7 updater user guide 7 18 2118 FWPD application not...

Page 50: ...ntities other than Teledyne SP Devices The warranty of replacement products shall terminate with the warranty of the product Buyer shall not return any products for any reason without the prior writte...

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