Teledyne SP Devices ADQ7DC, Manual

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2019-02-01
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ADQ7DC Manual
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ence to the sampling clock rate. The digitizer supports its specified sample rate only. This sample rate
can be tuned to allow phase locking to external equipment.
To reduce the sample-rate, a sample skip function is available.
Block diagrams of the clock network for ADQ7DC is given in
Figure 23 .
5.3 Front panel SMA connector
The front panel SMA connector is used for external clock reference input, direct external sampling clock
input or clock reference output. The input impedance is 50

to match the cable impedance. It can be
set to high impedance (200

) for using a bussed clock distribution (see Figure 13 ).
The high impedance mode allow that one digitizer can act as clock reference for two other digitizers. If
the source of the clock reference has a high power, more digitizers can be connected in the bussed net-
works.
5.4 Internal clock reference
The internal clock reference is a high accuracy VCTCXO at 10 MHz.
5.5 External clock reference
The free running internal clock reference of the digitizer offers high precision and is suitable for most
measurements. However, for some applications an absolute phase-lock to other parts of the system
may be necessary. To support that, the ADQ offers several options to accept an external clock refer-
ence. A long-term phase stability to other equipment is then guaranteed.
# DESCRIPTION USER COMMAND REF
a The SMA connector is common for external clock reference input,
external clock input and external reference output. SetClockInputImpedance 5.5
b Selecting the usage of the external connector is implicit from setting up
the clock system.
c The internal clock reference is a high performance VCTCXO. 5.4
d PXIe and MTCA.4 support clock reference from the backplane 5.5
e Select which clock reference source to use. SetClockSource
f The external clock reference is cleaned from jitter.
g The internal clock generator. 5.6
h Select which clock source to use SetClockSource 5.7
i Reduce sample rate with sample skip. SetSampleSkip 5.9
j Turn on clock reference output. Note that the connector is shared with the
clock reference input. EnableClockRefOut 5.8
Figure 23: ADQ7 clock network.
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