19-2233 PC2
2019-02-01
41(50)
ADQ7DC Manual
16-1796 PC2 2019-02-01
41(50)
Block diagram and timing of a streaming data transfer is in
. First, the entire
path for data processing, DMA, API and user’s application thread is set up to receive the data. Then the
acquisition is set up and armed by the user’s control thread.
In case of a burst trigger scenario, several records may be recored into the FIFO while the previous
records are transferred to the host PC. The FIFO will handle the load as long as the average data rate
is maintained within limits.
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DESCRIPTION
a
The A/D converter delivers a stream of data into the acquisition engine.
b
The acquisition engine applies triggers, headers, etc.
c
Data is sent in real-time to the FIFO on the ADQ.
d
The DMA is set up to transfer data to the PC.
e
Kernel buffers in the host PC receives the data form the digitizer.
f
The ADQAPI is set up to wait for incoming data and is ready to process it directly. The ADQAPI receives the
data and do necessary pre-processing, for example, lost packages, headers, and sends data to the user’s
buffers.
g
User’s buffers in RAM. These are accessed via API commands.
h
The user’s application thread is set up to wait for data and process the data as soon as it is available. This is
application specific code.
i
Example of output devices.
j
User’s control thread set up the system and starts and stops the user’s application thread. Note that only this
thread communicates with the digitizer.
Figure 33: Block diagram of triggered streaming acquisition and streaming data transfer.
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