Tektronix 070-9176-00, Instruction Manual

Page: 61 / 85

Performance Verification
46
P6467 High-Speed Probe Adapter Instruction Manual
11. Set the HFS 9003 Stimulus System test frequency to 100 MHz.
12. Select F1: START for and check that the logic analyzer does not trigger.
13. After ten seconds, select F1: STOP and check that the State Display menu
looks similar to the following repeating data sequence:
AAAA AA
5555 55
5555 55
AAAA AA
AAAA AA
5555 55
5555 55
AAAA AA
AAAA AA
5555 55
The acquired data for each column should be a repeating sequence as shown;
however, the data may not line up between the two columns as shown.
A failed test is indicated by wrong data.
14. Repeat steps 12 through 13 for each test frequency and clock lead delay
setting in Table 13.
Table 13: Test Setups for the DIV2 Operating Mode
P6467 Test
a
92A96 Probe
able
Te e ue
Clock Lead (C1) Delay
Board
Connection Cable
Connection
Test Frequency
Coaxial Cables Ribbon Cables
INPUT DATA B OUTPUT DATA B 100 MHz 3.1 ns 2.8 ns
INPUT DATA B OUTPUT DATA B 100 MHz 7.0 ns 7.3 ns
INPUT DATA B OUTPUT DATA B 165 MHz 7.0 ns 7.3 ns
INPUT DATA B OUTPUT DATA B 165 MHz 3.1 ns 2.8 ns
INPUT DATA B OUTPUT DATA B 195 MHz 3.1 ns 2.8 ns
INPUT DATA B OUTPUT DATA B 195 MHz 7.0 ns 7.3 ns
If you have coaxial probe cables, the Hold time is checked when you set the
LEAD DELAY of the data channels to 5 ns and the clock channel LEAD
DELAY to 3.1 ns (T
hold
= 1.9 ns). The Setup time is checked when you set the
clock channel LEAD DELAY to 7 ns (T
setup
= 2 ns).
If you have ribbon probe cables, the Hold time is checked when you set the
LEAD DELAY of the data channels to 5 ns and the clock channel LEAD
DELAY to 2.8 ns (T
hold
= 2.2 ns). The Setup time is checked when you set the
clock channel LEAD DELAY to 7.3 ns (T
setup
= 2.3 ns).