Tektronix 070-9176-00, Instruction Manual

Page: 60 / 85

Performance Verification
P6467 High-Speed Probe Adapter Instruction Manual
45
7. Check that the State Display menu looks similar to the following repeating
data sequence:
AAAA AA
5555 55
AAAA AA
5555 55
5555 55
AAAA AA
5555 55
AAAA AA
AAAA AA
5555 55
If the P6467 Probe acquires incorrect data, the logic analyzer will trigger and
display the faulty data.
NOTE . If you restored the logic analyzer setups from the setup file on the hard
disk, the display will show timestamps in addition to the data. The timestamps
are not required for these procedures.
8. Change the HFS 9003 Stimulus System clock channel (C1) LEAD DELAY
to 7.0 ns (7.3 ns if you have ribbon probe cables) and repeat steps
4 through 7.
9. Refer to Table 12 and repeat steps 4 through 8 for each test frequency and
clock lead delay.
Table 12: Test Setups for the NORM Operating Mode
P6467 Test
a
92A96 Probe
able
Te e ue
Clock Lead (C1) Delay
Board
e i
Cable
e i
Te e ue axial able Ribb able
Connection Connection
Test Frequency Coaxial Cables Ribbon Cables
INPUT DATA A OUTPUT DATA A 20 MHz 3.1 ns 2.8 ns
INPUT DATA A OUTPUT DATA A 20 MHz 7.0 ns 7.3 ns
INPUT DATA A OUTPUT DATA A 100 MHz 7.0 ns 7.3 ns
INPUT DATA A OUTPUT DATA A 100 MHz 3.1 ns 2.8 ns
INPUT DATA B OUTPUT DATA B 100 MHz 3.1 ns 2.8 ns
INPUT DATA B OUTPUT DATA B 100 MHz 7.0 ns 7.3 ns
INPUT DATA B OUTPUT DATA B 20 MHz 7.0 ns 7.3 ns
INPUT DATA B OUTPUT DATA B 20 MHz 3.1 ns 2.8 ns
10. Move jumpers J2 and J4 on the P6467 Probe to the DIV2 positions.