Tektronix 070-9176-00, Instruction Manual

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Operating Basics
P6467 High-Speed Probe Adapter Instruction Manual
23
CLKA/MSTR CLK
(J3)
EXT/MSTR CLK
(J1)
NORM/DIV2
(J4)
DIV2/NORM
(J2)
GND THLD
THLD
ADJ
F2
F1
Figure 13: P6467 Clock Jumpers and Clock Threshold Adjustment Locations
A description of each clock jumper follows:
H
J1 (MSTR CLK / EXT). This jumper connects either the Clock B Master
clock or an external clock from another P6467 probe to the 92A96 probe
cables connected to J200 (bottom two connectors) on the probe.
H
J2, J3 (NORM/DIV2). These two jumpers determine the operating mode of
the probe. Both jumpers must be in the same position. The NORM position
connects the input Master clock directly to the output drivers. The DIV2
position divides the clock frequency by two before sending the clock signal
to the output dividers.
H
J4 (CLK A/MSTR CLK). This jumper selects the clock source for the 92A96
probe cables connected to J100 (top two connectors) on the probe.
Use the Clock Threshold Adjustment (THLD ADJ) to set the threshold for the
clock inputs. Connect a digital voltmeter to test point THLD and ground and
adjust the THLD ADJ control for the desired threshold voltage. Figure 13 shows
the location of the THLD ADJ control and the THLD test point.