Tandberg Data
Introduction to the Drive
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2-6
Tandberg SLR Reference Manual
SCSI Controller
The Qlogic’s FAS368M is a multimode SCSI controller which in addition to supporting ULTRA
and Wide Ultra SCSI bus Single Ended mode, also supports Low Voltage Differential (LVD)
mode. The device complies with the SCSI-3 Parallel Interface 2 (SPI-2) X3.302 standard for
both modes.
Terminating the FASFAS368M for these modes must meet this standard.
Microprocessor Unit
The MC68331 is a member of the MC68000 family of the modular embedded controllers from
Motorola. The MC68331 combines high performance data manipulation capabilities with
powerful peripheral subsystems. The MCU is built up from standard modules that interface
through a common intermodule bus. The MCU incorporates a 32-bit CPU (CPU32), a system
integration module (SIM), a general purpose timer (GPT), and a queued serial module (QSM).
The MCU uses the 8/16-bit data bus to communicate with the digital circuits, and the SPI
(Synchronous Peripheral Interface) to communicate with the EEPROM and the Analog
ASICs.
The clock frequency is 25 MHz for the SLR60/75/100/140 and 16 MHz for the SLR7/50.
Data Path Controller
The DPC (Data Path Controller) is a digital ASIC designed by Tandberg Data which is
designed to communicate with the SCSI-controller, the data compression circuit, the data
buffer and the analog part of the Drive including the motors. The DPC has flow-through parity.
The DPC designed for SLR7/60/75/100/140 uses an integrated ALDC data compression core.
The DPC utilizes a 8MByte bank of SDRAM for the SLR7/60/75/100/140 and a 2MByte bank
of EDO DRAM for the SLR50.
Data Compression Circuit
The data compression circuit used in the Tandberg SLR Product Line Drives is the ALDC1-
20S-HA providing data compression based on the ALDC
(Adaptive Lossless Data
Compression)
algorithm which exhibits an average compression ratio of 2 to 1.
On the SLR7/60/75/100/140, the ALDC has been integrated in an ”in-line” configuration inside
the DPC ASIC, while on the SLR50, the stand-alone device has been implemented in a “look-
aside” fashion.
The ALDC algorithm has been accepted by several standardization organizations including
QIC.
Write Channel
The Write Channel is contained in a single ASIC featuring individual write current and Write
EQualization (WEQ) current programming for each of the write heads. The use of an ASIC
provides excellent signal symmetry.
The write channel features
“double fault protection/single fault detection”
to prevent unwanted
data overwrite and to provide very high data security.