Systran SCRAMNet+ VME3U, Hardware Reference Manual

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CSR DESCRIPTIONS
Copyright 1995, S
YS
I
RAN
Corp. 5-3 VME3U H/W REFERENCE
Table 5- CSR0 (Continued)
Bits General S Enable and Reset (READ/WRITE)
4 Auxiliary Control RAM Enable - When this bit is set, the ACR bytes are swapped in place of
the corresponding least-significant byte of every four-byte word in SCRAMNet
+
memory. The
values written to those ACR byte locations will dictate the type of interrupt that will occur when
the 4-byte memory location is written into. The ACR has five bits for interrupt control. They are
as follows:
ACR bit 0 - Receive Interrupt Enable - Setting this bit will generate an interrupt to the
host for network interrupt data received in this location.
ACR bit 1 - Transmit Interrupt Enable - Setting this bit will generate an interrupt to
the network for a host WRITE to this shared memory location.
ACR bit 2 - External Trigger 1 - Setting this bit will generate a trigger signal to an
external connector whenever there is a host READ/WRITE access to this shared
memory location.
ACR bit 3 - External Trigger 2 - Setting this bit will generate a trigger signal to an
external connector whenever there is a network WRITE to this shared memory location.
ACR bit 4 - HIPRO location enable - Setting this bit will cause the two 16-bit data or
four 8-bit items within the 32-bit address boundary to be transmitted as one 32-bit
network message. CSR2, bit 13 must also be set for this action to occur.
5 Interrupt On Memory Mask Match Enable - This bit must be set in order for any type of
memory interrupt to occur.
6 Override Receive Interrupt Enable Flag - When this bit is set, an interrupt will be generated
to the host by any interrupt data received from the network regardless of the status of the ACR
Receive Interrupt bit.
7 Enable Interrupt on Error - When this bit is set, Interrupt FIFO Full, Protocol Violation, Bad
Message and/or Receiver Overflow conditions will cause an interrupt request.
8 Network Interrupt Enable - This bit must be set to transmit interrupt data to the network.
9 Override Transmit Interrupt Enable Flag - When this bit is set, an interrupt will be sent out
on the network regardless of the status of the ACR Transmit Interrupt bit.