Systran SCRAMNet+ VME3U, Hardware Reference Manual

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OPERATION
Copyright 1995, S
YS
I
RAN
Corp. 4-27 VME3U H/W REFERENCE
In the event that the Transmit FIFO becomes full, the hardware will automatically extend
the next VME write cycle until the Shared-memory FIFO empties at least one message.
This prevents the loss of any data and is transparent to the user.
4.10.6 Write-Me-Last Mode
The Write-Me-Last mode of operation allows the originating node to be the last node in
the ring to have the data deposited to its memory. When the host performs a WRITE to
the SCRAMNet
+
shared-memory, it is not immediately written to the host memory, but
is first sent to the other SCRAMNet
+
nodes on the network.
Set CSR2, bits 7 and 8 to enable the Write-Me-Last mode. If desired, this mode can also
be used to generate interrupts to the originating node by setting CSR2, bit 9 as well.
CSR2, bit 7 is the Disable Host to Shared Memory Write.
4.11 Quad Switch
The Quad Switch is a switching center and is used to dynamically configure active
SCRAMNet and SCRAMNet
+
ring(s).
The Quad Switch provides dynamic configuration of up to five separate rings. Each
separate ring is connected to a port on the Quad Switch. Refer to Figure 4-10. Each ring
can be isolated from the other rings or can be included with one or more of the other
attached rings.
There is a single logical ring internal to the Quad Switch. The Quad Switch has 5 external
ports which allow access to this logical ring. Ports 1 through 4 are accessible on the front
of the Quad Switch cabinet. Port 5 access is at the rear of the cabinet.
All five ports have standard SCRAMNet transmitters and receivers. Each port can
transmit data to and receive data from the internal ring.
The Quad Switch is designed so that a port will be switched into the ring if all its
switching controls are enabled. Any one of the switching controls can cause the port to be
switched out.