Systran SCRAMNet+ VME3U, Hardware Reference Manual

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ACRONYM
Copyright 1995, S
YS
l
RAN
Corp. F-1 VME3U H/W REFERENCE
ACK Acknowledge or acknowledgment
ACR Auxiliary Control RAM
AS# Address Strobe number
BIST Built-In Self Test
BLT Block Transfer
CSR Control/Status Register
DPRC Dual Port RAM Controller
DS# Data Strobe #
DTACK Data Transfer Acknowledgment
DTB Data Transfer Bus
ECM Error Correction Mode
FDDI Fiber Distributed Data Interface
FIFO First-In, First-Out data buffer
FOB Fiber Optic Bypass
GB Gigabyte - 1024 Kilobytes ( a billion bytes)
I/O PAGE Block of address space which contains the CSRs for the processor and interface
devices
HACK Host Acknowledgment
HIPRO High Performance
HREQ Host Request
ISR Interrupt Service Routine
KB Kilobyte - 1024 bytes
LAN Local Area Network
LSFR Linear Feedback Shift Register
Longword 32-bit or 4-byte word
LSB Least Significant Byte or Bit
LSHLW Least Significant Half of a Longword
LSP Least Significant Portion
LSW Least Significant Word
MSB Most Significant Byte or Bit
MSHLW Most Significant Half of a Longword
MSP Most Significant Portion
MSW Most Significant Word
MTC Missing Transition Code
MWT SelBUS Memory Write Transfer cycle
NODE ID Network Node Identification number (0-255)
ns, ms,
µ
s Nanosecond, millisecond, microsecond; respectively
PCB Printed Circuit Board
PQFP Plastic Quad Flat Pack
RAM Random Access Memory
RMW Read-Modify-Write
ROAK Release On Interrupt Acknowledge cycle
SCM Shared Common Memory
SCRAMNet Shared Common Random Access Memory Network
SRAM Static Random Access Memory
ST AT&T Straight Tip type of fiber optic connector
UAT Unaligned Transfer