Systran SCRAMNet+ VME3U, Hardware Reference Manual

Page: 112 / 134

HOST ACCESS TIMING
Copyright 1995, S
YS
I
RAN
Corp. D-8 VME3U H/W REFERENCE
DTACK*
DSx*
HREQ
HACK
5
1 7
2
3 4
8
9
10
Cycle #1
1. AS to DSx = 10 ns (per VME Spec.)
2. DSx to HREQ = 80 ns (Host Adapter time)
3. HREQ = 6 ns (Host Adapter time)
4. End HREQ to End HACK = 133 ns DPRC)
5. HACK to DTACK = 22 ns (Host Interface)
6. DTACK to End of Cycle = 0 ns (per VME Spec.) 271 ns
7. Min. AS inactive = 30 ns (per VME Spec.)
Cycle #2
8. AS to DSx = 10 ns (per VME Spec.)
9. DSx to HREQ = 80 ns (Host Adapter time)
10. HREQ to End HACK = 257 ns (DPRC)
11. HACK to DTACK = 22 ns (Host Interface)
12. DTACK to End of Cycle = 0 ns (per VME Spec.) 399 ns
Figure D-7 Back-to-Back Host READs
Figure D-8 illustrates how the DPRC must manage two inputs. The network WRITEs
have the higher priority. Consequently, in this “worst case” scenerio, the Host READ
cycle is stretched.
B
U
S
HOST
LOGIC
N
E
T
W
O
R
K
HR
DTACK
HACK
ASIC
NW
DUAL PORT RAM CONTROLLER
MEMORY
HR
NW
Figure D-8 Back-to-Back Host READs
FIRST CYCLE
1. AS, DSx fall - Start of Cycle (80 ns delay to decode address).
2. HREQ asserted - READ request to DPRC.
3. Host interface logic sleeps until HACK is received from DPRC
(Maximum READ Time)
4. DPRC asserts HREQ_PEND Request accepted
- DPRC is backed up with two Network WRITEs
- DPRC performs READ for host.
5. HACK is issued to host interface logic.
6. DTACK is asserted - bus released.