Systran SCRAMNet+ VME3U, Hardware Reference Manual

Page: 54 / 134

OPERATION
Copyright 1995, S
YS
I
RAN
Corp. 4-28 VME3U H/W REFERENCE
Figure 4-11 Interrupt Service Routine
CSR0 MME and HIE must be set in order to re-arm interrupts.
CSR1 Bits 0-15 contain various error and status conditions. Interrupts are re-armed whenever any
value is written to CSR1.
CSR4 Bits 0-15 contain the interrupt address bits A0-A15.
CSR5 Bits 0-6 contain the interrupt address bits A22-A16.
Bit 15 contains the Interrupt FIFO Not Empty status.
CSR6 Bits 0-7 contain the interrupt vector.
If an interrupt has been received by the host processor from the SCRAMNet
+
Network interrupt logic
and the appropriate interrupt vector has been initialized in CSR6, then the Interrupt Service Routine
linked to that vector will be invoked. Interrupts will be disabled until re-armed by writing to CSR1.
Until that time, all other interrupts will be written into the Interrupt FIFO where they can be processed
in the Interrupt Service Routine.
If Interrupts on Errors is enabled, then an interrupt due to an error has occurred if the interrupt FIFO is
empty on the initial check of CSR5 in the Interrupt Service Routine.
Read CSR5
Test the Interrupt FIFO Not Empty status bit 15
If (Interrupt FIFO is Empty)
Read CSR1 to determine the error condition(s)
Respond to any error conditions
End if
While (Interrupt FIFO is NOT Empty)
Save interrupt address bits A22-A16 from CSR5 (from previous read)
Read CSR4 and save interrupt address bits A15-A0
• • •
Service interrupt according to interrupt address data or address
• • •
Read CSR5 and save Interrupt FIFO Empty status
Endwhile
Write to CSR1 to re-enable interrupts
Return from interrupt service routine