Systran SCRAMNet+ VME3U, Hardware Reference Manual

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Copyright 1995, S
YS
I
RAN
Corp. 3-1 VME3U H/W REFERENCE
3. 0 DESCRIPTION
3.1 Overview
The SCRAMNet
+
Network is a real-time communications network, based on a
replicated, shared-memory concept. Each host processor on the network has access to its
own local copy of shared memory which is updated over a high-speed, serial-ring
network. It is optimized for the high-speed transfer of data among multiple, real-time
computers that are all solving portions of the same real-time problem. The SCRAMNet
+
node board can automatically filter out redundant data.
3.2 Shared Memory
In its simplest form, the SCRAMNet
+
Network system is designed to appear as general-
purpose memory. The use of this memory depends only on the conventions and
limitations imposed by the specific host computer system and operating system. On most
processors, this means that the application program can use this memory in basically the
same way as any other data storage area of memory. The memory cannot be used as
instruction space.
The major difference between SCRAMNet
+
memory and system memory is that any
data written into SCRAMNet
+
memory is automatically sent to the same SCRAMNet
+
memory location in all nodes on the network. This is why it is also referred to as
replicated shared memory. A good analogy is the COMMON AREA used by the
FORTRAN programming language. Where the COMMON AREA makes variables
available to subroutines of a program, SCRAMNet
+
makes variables available to
processors of a network.
The SCRAMNet
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memory size can range from 128 KB on-board memory to 8 MB of
expansion memory. Available options include: 128 KB, 512 KB, 1 MB, 2 MB, 4 MB and
8 MB. No software driver is required except for interrupt handling. When a host
computer writes to the shared memory, the proper handshaking for a memory card is
supplied by the SCRAMNet
+
node host adapter. The shared memory behaves somewhat
like resident or local memory.
3.2.1 Dual Port Memory Controller
The Dual Port Memory Controller (see Figure 2-1) allows the host to READ from or
WRITE to shared memory with a simultaneous network WRITE to shared memory.
Unless an interrupt has been authorized for that memory address, the host is not aware the
network is writing to shared memory. This is why caching must be disabled for
SCRAMNet memory. If an interrupt has been authorized, the interrupt will then be sent
to the host processor.
3.2.2 Control/Status Registers (CSRs)
The operation of the SCRAMNet
+
board is controlled by 17 Input/Output (I/O) CSRs.
The location of the CSRs in the computer’s address space is switch selectable. In most